SurfNoC

Abstract

As multicore processors find increasing adoption in domains such as aerospace and medical devices where failures have the potential to be catastrophic, strong performance isolation and security become first-class design constraints. When cores are used to run separate pieces of the system, strong time and space partitioning can help provide such guarantees. However, as the number of partitions or the asymmetry in partition bandwidth allocations grows, the additional latency incurred by time multiplexing the network can significantly impact performance.In this paper, we introduce SurfNoC, an on-chip network that significantly reduces the latency incurred by temporal partitioning. By carefully scheduling the network into waves that flow across the interconnect, data from different domains carried by these waves are strictly non-interfering while avoiding the significant overheads associated with cycleby-cycle time multiplexing. We describe the scheduling policy and router microarchitecture changes required, and evaluate the information-flow security of a synthesizable implementation through gate-level information flow analysis. When comparing our approach for varying numbers of domains and network sizes, we find that in many cases SurfNoC can reduce the latency overhead of implementing cycle-level non-interference by up to 85%.

A Survey of Timing Channels and Countermeasures

“…So low-security application cannot imply any information about high-security application using congestion in NoC and hence timing channel is mitigated. An on-chip network called SurfNoC is proposed in [Wassel et al 2013] to reduce the latency due to temporal partitioning. They have introduced a scheduling 0:25 Table XIII.…”

“…Hardware based Fuzzy time [Hu 1991] Modified architecture [Ciet et al 2003;Hodjat et al 2005] [Ghosh et al 2011;Ghosh and Verbauwhede 2014] Random delay [Cilio et al 2010;Cilio et al 2013] NoC architecture [Wang and Suh 2012;Wassel et al 2013] Memory controller Using GLIFT Implementation [Tiwari et al 2009;] ] Theoretical analysis [Oberg et al 2010;Hu et al 2012] policy and router micro-architecture to allow data from different domains to flow in a strictly non-interfering manner. Wang et al have proposed a memory controller that allows mutually mis-trusting parties to share main memory securely by eliminating memory timing channels .…”

Probabilistically time-analyzable complex processor designs

“…This is generally unaffordable when cache memories are used for 6.6 Conclusions performance purposes due to the difficulties to schedule, for instance, cache misses. A number of works have focused on providing tight bounds for the worst-case traversal time in complex NoCs such as meshes [Rahmati et al (2013),Psarras et al (2015, Wassel et al (2013), Panic et al (2016b)].…”