Topology adaptive network-on-chip design and implementation

Abstract

Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is proposed that is highly scalable, and can be easily changed to accomodate various needs. A network-on-chip design, realised as part of the platform that the authors are developing for reconfigurable systems, is presented. This design is suitable for building networks with irregular topologies, and with low latency and high throughput.

FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology

“…There are many proposed topologies in the literature, as cited in previous section each topology designs offers a different set of tradeoffs in terms of metrics, such as network degree, network extendibility notice in which a 2D mesh [17] topology provides very good theoretical metrics. Nevertheless, due to the increasing complexity of application, this topology cannot provide a good performance.…”

Customizing Reconfigurable On-Chip Crossbar Scheduler

“…In [6], single 2D-mesh packet router for an 8-bit flit occupies 352 slices and 10 block memories (BRAMs) in a Virtex-II Pro (xc2vp30) device. Our work is close to [7], in which a topology adaptive parameterized network component is presented. While the crossbar interconnects inside a router of [6] [7] are still all-to-all, the physical topology of our crossbar interconnects is identical to the logical topology of the application.…”

“…Our work is close to [7], in which a topology adaptive parameterized network component is presented. While the crossbar interconnects inside a router of [6] [7] are still all-to-all, the physical topology of our crossbar interconnects is identical to the logical topology of the application. Finally, our custom scheduling scheme differs from traditional traffic-specific scheduling schemes, such as a weighted round-robin, in that our scheduler does not arbitrate unnecessary interconnects.…”

“…Our scheduler is different from the schedulers in ASIC-targeted NoC routers, since our network topology is reconfigurable on demand and our scheduler utilizes the reconfigurability. NoCs targeting FPGAs (for example, [5][6] [7]) employ fixed topologies defined at design-time. The topology is defined by the interconnections between routers and the crossbar inside the router also accommodates internally all-to-all physical interconnects.…”

Efficient simulation and modelling of non-rectangular NoC topologies

“…A number of papers on constructing irregular network topologies [4], [5], [6], [7] and developing NoC simulators [8], [9], [10], [11], [12] have been published in the past decade. Several design methods were proposed for constructing either special irregular topologies: Ring, Octagon and 2-hop or custom irregular networks tailored to specific applications.…”