Top Level SOC Interconnectivity Verification Using Formal Techniques

Roy, Subir Kumar

doi:10.1109/mtv.2007.22

Cited by 12 publications

(3 citation statements)

References 4 publications

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“…It is also possible to use assertions to prove that the connectivity inside a SoC is correctly implemented. As an example, Roy [62] presents a tool to automatically generate assertions from a spreadsheet and formally verify the connectivity between the blocks of a SoC using ABV on Cadence Incisive Formal Verifier, which is SMC-based. One great disadvantage of this tool, though, is the necessity to create the input spreadsheet manually.…”

Section: Discussionmentioning

confidence: 99%

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

2018

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The high degree of miniaturization in the electronics industry has been, for several years, a driver to push embedded systems to different fields and applications. One example is safety-critical systems, where the compactness in the form factor helps to reduce the costs and allows for the implementation of new techniques. The automotive industry is a great example of a safety-critical area with a great rise in the adoption of microelectronics. With it came the creation of the ISO 26262 standard with the goal of guaranteeing a high level of dependability in the designs. Other areas in the safety-critical applications domain have similar standards. However, these standards are mostly guidelines to make sure that designs reach the desired dependability level without explicit instructions. In the end, the success of the design to fulfill the standard is the result of a thorough verification process. Naturally, the goal of any verification team dealing with such important designs is complete coverage as well as standards conformity, but as these are complex hardware, complete functional verification is a difficult task. From the several techniques that exist to verify hardware, where each has its pros and cons, we studied six well-established in academia and in industry. We can divide them into two categories: simulation, which needs extremely large amounts of time, and formal verification, which needs unrealistic amounts of resources. Therefore, we conclude that a hybrid approach offers the best balance between simulation (time) and formal verification (resources).

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Section: Discussionmentioning

confidence: 99%

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

2018

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“…This becomes major bottleneck for SoC verification where the multiple revision of pinmux is quite obvious in today's SoC, which is designed in competition driven market place. [10] helps to perform static verification [3] of the pinmuxing implementation. But for dynamic verification [4] (i.e directed, random, performance testing etc), there is a need to re-build the testbench/testcases (as per new pinmux) which impacts the overall verification cycle time.…”

Section: Limitation Of Traditional Approachmentioning

confidence: 99%

A method to make SoC verification independent of pin multiplexing change

Ghosh¹,

Hira²,

Garg³

2013

2013 International Conference on Computer Communication and Informatics

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As the size and complexity of System-On-Chip (SoC) design is increasing rapidly, a portable and structured verification (testbench) environment is desired to cope with time to market. The pin multiplexing complexity i.e number of functions/peripherals (IPs) multiplexed on a single I/O pad is growing rapidly as many functions/IPs are getting integrated into single device. There are SoCs where four or more functions/peripherals are multiplexed on a single chip pad as the application usage of each IP/function is mutually exclusive in nature. This pin multiplexing option changes across SoCs and also in between different releases for the same SoC. Over time, it is being observed that this I/O pad multiplexing becomes major bottleneck in reusing/porting/creating testbench and verification environment across SoCs and releases. In this paper, we are proposing a new testbench layer (i.e "Function mapping") in between the device under verification(DUV) and the various testbench components (e.g testbench drivers/ testbench monitors/bus functional models). This new layer reduces the overall verification cycle time significantly (approx 20% to 50%). We will discuss this layer implementation and usage in detail and results of the proposed approach.

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“…This automated usage is also applicable at the SOC level, for the verification of chip-level connectivities [7], e.g. IPconnectivity, pin-muxing, boundary pads, DFT connectivity, etc.…”

Section: Designermentioning

confidence: 99%

Strategies for mainstream usage of formal verification

Mitra

2008

Proceedings of the 45th Annual Design Automation Conference

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Formal verification technology has advanced significantly in recent years, yet it seems to have no noticeable acceptance as a mainstream verification methodology within the industry. This paper discusses the issues involved with deploying formal verification on a production mode, and the strategies that may need to be adopted to make this deployment successful. It analyses the real benefits and risks of using formal verification in the overall verification process, and how to integrate this new technology with traditional technologies like simulation. The lessons described in this paper have been learnt from several years of experience with using commercial formal verification tools in industrial projects.

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Top Level SOC Interconnectivity Verification Using Formal Techniques

Cited by 12 publications

References 4 publications

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

A method to make SoC verification independent of pin multiplexing change

Strategies for mainstream usage of formal verification

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