To DFM or not to DFM?

Tam, Wing Chiu; Blanton, R. D.

doi:10.1145/2024724.2024740

Cited by 24 publications

(25 citation statements)

References 19 publications

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“…The methodologies developed include evaluating the effectiveness of DFM (design-for-manufacturability) rules [24] in systematic-defect prevention, identifying and understanding systematic defects [25] to guide process improvement effort, formulate new DFM rules [26] or identify targets for test [22,27], and creating a framework for fast and accurate defect simulation [28] to validate these and other emerging test/yield learning methodologies (e.g., [29]). for the three shaded bubbles in Figure 5, which indicate the three problems addressed in this dissertation.…”

Section: This Is Illustrated Inmentioning

confidence: 99%

“…Since X 10 and X 00 appears in the numerator and denominator of the odds ratio expression, respectively, their effect will be cancelled out. It should be noted that a different metric was used in the earlier version of RADAR [63]. When performing validation of RADAR using simulation experiments (to be discussed in detail in Section 2.4.2), it is found that, while the earlier metric gave the correct rule ranking, it cannot be reliably interpreted because it is dependent on the amount of passing data collected and therefore is not invoked here.…”

Section: Relative Risk Estimationmentioning

confidence: 99%

“…However, the details of this analysis are beyond the scope of this work. If the systematic defects identified are found to have a significant yield impact, then the corresponding DFM rules can be provided to the designers so that they can be deployed in future designs [26,63].…”

Section: Simulation Validationmentioning

confidence: 99%

“…On-going diagnoses are used as yield learning techniques to identify systematic defects [25,39,49,[73][74][75]82] and derive important information that includes, for example, design-feature failure rates [76,77]. In [24,78], the effectiveness of a given set of DFM rules is evaluated using volume diagnosis results. Diagnosis is also used as a part of a yield-monitoring vehicle 6 A systematic defect can be due to the fabrication process only or due to interactions between the design and the process.…”

Section: Chapter 4 Defect Simulationmentioning

confidence: 99%

“…For example, on-going diagnoses are used to identify systematic defects [25,49,[73][74][75] and derive design-feature failure rates [76,77]. In [24,78], the effectiveness of DFM is evaluated using volume diagnosis results. Diagnosis is also used as a part of a yieldmonitoring vehicle for estimating defect density and size distributions (DDSDs) [79].…”

Section: Introductionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Section: This Is Illustrated Inmentioning

confidence: 99%

Section: Relative Risk Estimationmentioning

confidence: 99%

Section: Simulation Validationmentioning

confidence: 99%

Section: Chapter 4 Defect Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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Automatic Layout Optimizations for Integrated MOSFET Power Stages

Guilherme

Horta

2015

Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design

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This chapter presents a design automation approach that generates automatically error-free area and parasitic optimized layout views of output power stages consisting of multiple power MOSFETs. The tool combines a multitude of constraints associated with DRC, DFM, ESD rules, current density limits, heat distribution, and placement. It uses several optimization steps based on evolutionary computation techniques that precede a bottom-up layout construction of each power MOSFET, its optimization for area and parasitic minimization, and its optimal placement within the output stage power topology network. IntroductionIn integrated audio power stages or power management units (PMG), it is necessary to design the layout of power transistors, but due to several technology design constraints and lack of investment in dedicated tools, this task has been mainly manual. Multiple constraints had hampered approaches based on parametric cells (pcells), respectively:• Design kits do not supply transistor pcells meeting ESD rules and guidelines;• Electromigration constraints of maximum current densities on metal tracks, vias, and contacts [1, 2]; • Design and manufacturing rules (DFM) specifically related with metal stress relief and etching effects [3].

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