Automatic Layout Optimizations for Integrated MOSFET Power Stages

Abstract

This chapter presents a design automation approach that generates automatically error-free area and parasitic optimized layout views of output power stages consisting of multiple power MOSFETs. The tool combines a multitude of constraints associated with DRC, DFM, ESD rules, current density limits, heat distribution, and placement. It uses several optimization steps based on evolutionary computation techniques that precede a bottom-up layout construction of each power MOSFET, its optimization for area and parasitic minimization, and its optimal placement within the output stage power topology network. IntroductionIn integrated audio power stages or power management units (PMG), it is necessary to design the layout of power transistors, but due to several technology design constraints and lack of investment in dedicated tools, this task has been mainly manual. Multiple constraints had hampered approaches based on parametric cells (pcells), respectively:• Design kits do not supply transistor pcells meeting ESD rules and guidelines;• Electromigration constraints of maximum current densities on metal tracks, vias, and contacts [1, 2]; • Design and manufacturing rules (DFM) specifically related with metal stress relief and etching effects [3].