This paper presents a thermal-aware floorplaning tool for integrated MOSFET power stages. It generates area and power optimized transistors, automatically complying with design rules. The tool also creates placement solutions of power stages, optimizing for area, wire-length and temperature spread. The tool creates technology independent layouts, and directly export designs into GDSII format, allowing complete independence from IC design platforms. A brief comparison of floorplanning techniques, embedded in this tool, is presented for several generally known benchmarks. The device layout and thermal-aware floorplaning capabilities are demonstrated and compared with manual designs of a half-bridge power stage for a Class-D amplifier, and a manually optimized device layout in a DC-DC buck converter stage -the tool results exhibit lower resistance and dynamic power losses while speeding-up the design flow by orders of magnitude.
This paper presents an automatic layout generation tool for power MOSFET transistors in bulk CMOS. It is implemented in an open multiplatform language, Python, and is capable of generating area and power optimized transistors, which automatically meet DRC, DFM and ESD rule sets. The tool is able to fast create technology independent layouts, easily ported between technology nodes, and directly export designs into GDSII format, allowing complete independence from any IC design platform. The tool is demonstrated in a design of a halfbridge power stage for a Class-D amplifier and compared with a reference manual design -the results obtained are superior: lower resistance and dynamic power losses, while keeping almost the same overall area but speeding-up the design flow by several orders of magnitude.
This chapter presents a design automation approach that generates automatically error-free area and parasitic optimized layout views of output power stages consisting of multiple power MOSFETs. The tool combines a multitude of constraints associated with DRC, DFM, ESD rules, current density limits, heat distribution, and placement. It uses several optimization steps based on evolutionary computation techniques that precede a bottom-up layout construction of each power MOSFET, its optimization for area and parasitic minimization, and its optimal placement within the output stage power topology network.
IntroductionIn integrated audio power stages or power management units (PMG), it is necessary to design the layout of power transistors, but due to several technology design constraints and lack of investment in dedicated tools, this task has been mainly manual. Multiple constraints had hampered approaches based on parametric cells (pcells), respectively:• Design kits do not supply transistor pcells meeting ESD rules and guidelines;• Electromigration constraints of maximum current densities on metal tracks, vias, and contacts [1, 2]; • Design and manufacturing rules (DFM) specifically related with metal stress relief and etching effects [3].
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