TLP calibration, correlation, standards, and new techniques [ESD test]

Barth, Jon; Verhaege, K.; Henry, L.; Richner, John

doi:10.1109/eosesd.2000.890031

Cited by 32 publications

(7 citation statements)

References 13 publications

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“…A common ESD event referred to as the human body model (HBM) is widely used to characterize device reliability when the charge in the human body is being transferred to the ground through integrated circuits. In addition, transmission line pulse (TLP) testing can provide reference for critical parameters in the ESD circuit [2][3][4]. Thus, testing with a combination of HBM and TLP is common practice [5,6].…”

Section: Introductionmentioning

confidence: 99%

Analysis of HBM Failure in 3D NAND Flash Memory

Song

Li²,

Wang³

et al. 2022

Electronics

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers’ local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness.

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Section: Introductionmentioning

confidence: 99%

Analysis of HBM Failure in 3D NAND Flash Memory

Song

Li²,

Wang³

et al. 2022

Electronics

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“…The design becomes especially challenging for the fast charged device model (CDM) ESD model [2], and Socket CDM (SDM) [3], where the turn-on speed of ESD protection is of great importance [4]. TLP (Transmission Line Pulsing) testers [5][6], Very-Fast TLP (VF-TLP) [7] and modified VF-TLP [8] testers, and Capacitively-Coupled TLP (CC-TLP) [9] testers are invented as a pulse type curve tracer to measure the current-voltage characteristics of ESD devices. A great number of theoretical analysis and Technology CAD (TCAD) simulation approaches have also been proposed to investigate the transient switching behaviour of protection transistors [10][11], but the simulations need to be carefully calibrated using experimental measurements.…”

Section: Introductionmentioning

confidence: 99%

Study of turn-on characteristics of SCRs for ESD protection with TDR-O and TDR-S TLPs

Huo

Han

et al. 2010

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

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There are few good evaluation methods to evaluate CDM ESD protection performance such as device turn-on speed, etc. A new current-waveform-based method to evaluate the turn-on speed of an ESD protection device is proposed. The method uses two Transmission-Line Pulse (TLP) Tester to investigate the turn-on characteristics of SCR and related devices. Both intrinsic and normalized turn-on conditions are defined for protection devices to study the different factors that affect the turn-on characteristic under various conditions. The turn-on of both forwardly and reversely working of devices is measured for the CDM model including positive and negative currents. From the experimental results, it is concluded that NMLSCR's performance is superior to PMLSCR in turn-on speed; MLSCR requires higher It1 to be turned on; and the turn-on speed of a PMLSCR decreases significantly with small increases in pulse amplitude under intrinsic working condition while NMLSCR and LSCR do not exhibit such property.

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“…In order to interpret the result of VFTLP test in terms of CDM qualification, the correlation between the passing levels of CDM and VFTLP is indispensible. The correlation between qualification test and TLP test has been demonstrated between HBM and TLP [1][2][3][4][5], and between HMM and TLP [6]. However, the difference between CDM and VFTLP tests is significant, which makes the correlation between them more challenging to find than that of HBM and TLP.…”

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confidence: 97%

Correlation of very fast transmission line pulse (VFTLP) and Field-Induced Charged Device Model (CDM) Testing

Xue

2012

2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

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The correlation between the second break down current of VFTLP Testing and the passing voltage of Field-Induced CDM Testing has been derived. The derivation is based on the power to failure relation and RLC model of CDM test. The derived correlation has been also demonstrated in experiment. I. BACKGROUNDField-Induced Charged Device Model (CDM) has been widely applied for the CDM qualification test in the industry. However, the CDM test is unable to characterize the operational response of ESD protection devices. The need for device characterization is well met by Very Fast Transmission Line Pulse (VFTLP) test instead. In order to interpret the result of VFTLP test in terms of CDM qualification, the correlation between the passing levels of CDM and VFTLP is indispensible. The correlation between qualification test and TLP test has been demonstrated between HBM and TLP [1][2][3][4][5], and between HMM and TLP [6]. However, the difference between CDM and VFTLP tests is significant, which makes the correlation between them more challenging to find than that of HBM and TLP. II. CDM MODELINGAtwood et al. [2] proposed a three capacitor model for CDM tester. This model has been applied in the simulation of CDM test and sees good approximation [7]. The schematic of the model is shown in Figure 1. C_DUT denotes the capacitance between the Device Under Test (DUT) with the field plate of the CDM tester; C_DG denotes the capacitance between DUT and the ground plate; and C_FG denotes the capacitance between the ground plate and the field plate. Switch S1 represents the pogo pin connecting ground plate and DUT; L1 and R2 represent the parasitic inductance and resistance in the discharging path. During the charging phase of CDM test, S1 remains open and the three capacitors namely C_DUT, C_DG, and C_FG are charged up between high voltage V_CDM and Ground. When discharge occurs, the S1 closes forming a low impedance path to Ground and the capacitors are discharged. Fig. 1. Three Capacitor ModelThe RLC circuit is solved as follows:The current in discharging pass isis therefore,· 1 ( ) 2 C_DUT S1 V_CDM R1 100e6 L1 C_FG C_DG R2

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TLP calibration, correlation, standards, and new techniques [ESD test]

Cited by 32 publications

References 13 publications

Analysis of HBM Failure in 3D NAND Flash Memory

Analysis of HBM Failure in 3D NAND Flash Memory

Study of turn-on characteristics of SCRs for ESD protection with TDR-O and TDR-S TLPs

Correlation of very fast transmission line pulse (VFTLP) and Field-Induced Charged Device Model (CDM) Testing

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