Timing yield estimation from static timing analysis

Gattiker, A.; Nassif, Sani R.; Dinakar, R.; Long, Cheng

doi:10.1109/isqed.2001.915268

Cited by 88 publications

(76 citation statements)

References 5 publications

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“…Furthermore, these variations are increasing with each new generation of technology. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under such types of uncertainty, and has been the subject of intense research recently [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The result of SSTA is the prediction of parametric yield at a given target performance for a design.…”

Section: Introductionmentioning

confidence: 99%

An accurate sparse-matrix based framework for statistical static timing analysis

et al. 2012

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Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

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Section: Introductionmentioning

confidence: 99%

An accurate sparse-matrix based framework for statistical static timing analysis

et al. 2012

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“…As part of circuit timing verification, one has to leave enough margin so that circuit delay variations do not affect yield too adversely. We will focus on this part of the overall yield problem, referred to as timing yield or circuit-limited yield [1,2].…”

Section: Introductionmentioning

confidence: 99%

“…Also, the corner based method can be too conservative and does not provide the user with any quantitative feedback on the robustness of the design [3]; it is a pass/fail approach. Furthermore, this traditional approach cannot handle within-die statistical variations [2]. On the other hand, for microprocessors, where nominal process files are used and a timing margin needs to be left as slack, there are no easy ways to decide what the margin should be, to account for within-die variations which have become important recently [1].…”

Section: Introductionmentioning

confidence: 99%

“…Recently, due to the increased importance of within-die variations, there has been an increased interest in tackling the timing yield problem by employing statistical techniques as part of the circuit timing analysis step [2,1,4,5,6]. The aim is to include statistical delay variations as an extension to traditional STA leading to statistical static timing analysis (SSTA).…”

Section: Introductionmentioning

confidence: 99%

“…In a number of cases [2,6,7,8], it has been assumed that within-die variations are totally uncorrelated, an assumption which is not true in practice. It is usually hard to express the correlations between within-die parameter variations with a model built from process data.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Statistical timing analysis with two-sided constraints

Heloue¹,

Najm²

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a "device file setting" that takes into account within-die statistical variations, and with which to run traditional static timing analysis in order to meet the desired yield. Using process-specific "generic paths" representing critical paths in a given process technology, our approach can be used early in the design process, most importantly during the pre-placement phase. Within-die variations are taken care of using a simple model that assumes positive correlation, which leads to upper and lower bounds on the timing yield. Our approach also handles both setup and hold timing constraints.

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Statistical Static Timing Analysis

Li¹,

Schlichtmann²

Timing

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Timing yield estimation from static timing analysis

Cited by 88 publications

References 5 publications

An accurate sparse-matrix based framework for statistical static timing analysis

An accurate sparse-matrix based framework for statistical static timing analysis

Statistical timing analysis with two-sided constraints

Statistical Static Timing Analysis

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