Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment

Joshi, Prasad; Beerel, Peter A.; Roncken, Marly; Sutherland, Ivan E.

doi:10.1007/978-3-642-11512-7_17

Cited by 6 publications

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since the introduction of logical effort, many researchers have used the logical effort to calculate the effect of process type [12], transistor size, topology [13] of a specific circuit performance and power consumption [14]. Prasad Joshi and Peter A. Beerel [15] have directly used logical effort to reason about the timing of 6-4 GasP asynchronous NoC control circuits, and constructed a test chip called "Infinity" to support for this analytical prediction.…”

Section: Related Workmentioning

confidence: 99%

A method of customizing GasP with logical effort

Wang,

Li,

et al. 2023

Eighth International Symposium on Advances in Electrical, Electronics, and Computer Engineering (ISAEECE 2023)

View full text Add to dashboard Cite

The GasP circuit is a high-speed controller that has been used more often in the field of asynchronous circuits. However, in the conventional GasP design method, the matching process of its internal delay lacks the consideration of the circuit application environment. In view of this, this paper proposes three delay adjustment methods by combining the usage scenario of the circuit and the logical effort. The method first adjusts the pulse width of the digital circuit, the ability to drive the DFF and the maximum equivalent frequency of the circuit, then customizes the delay and drive of the GasP, and finally verifies the performance with a NoC built with the GasP. The experimental results show that the maximum equivalent frequency of GasP can reach 2.28GHz in 110nm CMOS process, which is about 10 times of the classical synchronous design.

show abstract