Long-Range GasP with Charge Relaxation

Gilla, Swetha Mettala; Roncken, Marly; Sutherland, Ivan E.

doi:10.1109/async.2010.26

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…It is vital to use distributed wire models when studying long links, in order to avoid unrealistically optimistic results [5]. As a concrete example: STATS transceivers sense the state of the wire locally to determine when to stop driving.…”

Section: A Planar Linksmentioning

confidence: 99%

“…In order to keep shrinking BEOL features without dramatically increasing wire resistance, chip foundries have increased the cross-sectional height of wires. The resistance of long wires can no longer be ignored-the lumped capacitor model is no longer valid in deep-submicron technologies [5]. Furthermore, taller, more closely spaced wires have resulted in large coupling capacitance values, increased crosstalk, and decreased performance.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Bit of Analysis on Self-Timed Single-Bit On-Chip Links

Tse

Hill

Manohar

2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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Abstract-We present a study of five different self-timed singlebit on-chip links implemented in 90 nm, 65 nm, and 45 nm process technologies. These include representative examples of Quasi Delay-Insensitive, single-track, ternary, and voltage-scaled links, as well as a link of our own design intended to minimize wire usage. We characterize the tradeoffs between throughput, energy, and area for planar wiring as well as 3D throughsilicon vias. We also describe our multi-objective optimization framework for exploring this parameter space.

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Section: A Planar Linksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Bit of Analysis on Self-Timed Single-Bit On-Chip Links

Tse

Hill

Manohar

2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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“…presence of a token, and its output or "successor" state-wire is low, indicating a space or "vacancy". This condition produces a pulse on the fire signal that advances the token [3,4]. Tokens can change their spacing on the FIFO but not their sequence.…”

Section: Chapter 1 Introduction and Backgroundmentioning

confidence: 99%

Drafting in Self-Timed Circuits

Cowan

2019

IEEE Trans. VLSI Syst.

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Intervals between data items propagating in self-timed circuits are controlled by handshake signals rather than by a clock. In many self-timed designs, a trailing data item will catch up with a leading item or token, even when it trails by thousands of gate delays. This effect, called "drafting," can be seen in many of the self-timed designs, e.g., GasP, Mousetrap, Click, and Micropipeline. The purpose of this dissertation is to reveal the circuit mechanism of drafting in self-timed circuits typically used in FIFO stages.Drafting is usually considered to be incidental to the operation of self-timed circuits since interval timing information is irrelevant to preservation of the proper order of data.However, if new applications of self-timed designs require preservation of timing between data items, or if interval data carries information, then the drafting mechanism must be understood to control it. Since drafting is an analog function in a digital circuit the effect may be used as a source of randomness or uniqueness. The drafting effect changes with manufacturing variability and each unit may provide a source for a unique digital signature that can be used in security applications.ii

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Naturalized Communication and Testing

Roncken

Gilla

Park

et al. 2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

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We "naturalize" the handshake communication links of a self-timed system by assigning the capabilities of filling and draining a link and of storing its full or empty status to the link itself. This contrasts with assigning these capabilities to the joints, the modules connected by the links, as was previously done. Under naturalized communication, the differences between Micropipeline, GasP, Mousetrap, and Click circuits are seen only in the links -the joints become identical; past, present, and future link and joint designs become interchangeable.We also "naturalize" the actions of a self-timed system, giving actions status equal to states -for the purpose of silicon test and debug. We partner traditional scan test techniques dedicated to state with new test capabilities dedicated to action. To each and every joint, we add a novel proper-start-stop circuit, called MrGO, that permits or forbids the action of that joint. MrGO, pronounced "Mister GO," makes it possible to (1) exit an initial state cleanly to start circuit operation in a delay-insensitive manner, (2) stop a running circuit in a clean and delay-insensitive manner, (3) single-or multi-step circuit operations for test and debug, and (4) test sub-systems at speed.

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Long-Range GasP with Charge Relaxation

Cited by 6 publications

References 11 publications

A Bit of Analysis on Self-Timed Single-Bit On-Chip Links

A Bit of Analysis on Self-Timed Single-Bit On-Chip Links

Drafting in Self-Timed Circuits

Naturalized Communication and Testing

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