A Framework for Asynchronous Circuit Modeling and Verification in ACL2

Chau, Cuong; Hunt, Warren A.; Roncken, Marly; Sutherland, Ivan E.

doi:10.1007/978-3-319-70389-3_1

Cited by 6 publications

(3 citation statements)

References 10 publications

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“…Unrolling the circuit to capture its behavior, in this case, is not straightforward. Formal analysis of such fully asynchronous circuits is a topic of ongoing research [20] and outside the scope of this paper.…”

Section: Frequency Fractionsmentioning

confidence: 99%

A Security Analysis of Circuit Clock Obfuscation

et al. 2022

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Key-based circuit obfuscation or logic-locking is a technique that can be used to hide the full design of an integrated circuit from an untrusted foundry or end-user. The technique is based on creating ambiguity in the original circuit by inserting “key” input bits into the circuit such that the circuit is unintelligible absent a correct secret key. Clock signals have traditionally been avoided in locking in order to not corrupt the timing behavior of the locked circuit. In this paper, we explore the case where the clock signal itself may be obfuscated by ambiguating its frequency or pattern. Along with discussing formal notions of security in this context, we present practical ways to deobfuscate such designs using techniques from multi-rate model-checking. We present experimental data on deobfuscation runtime on a set of sequential benchmark circuits. Our results show that naive random clock obfuscation may not provide more security per overhead than traditional random keyed-gate insertion. We discuss how clock obfuscation may be a more attractive choice for special circuit designs that are inherently multi-clock/asynchronous.

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Section: Frequency Fractionsmentioning

confidence: 99%

A Security Analysis of Circuit Clock Obfuscation

et al. 2022

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“…VHDL libraries for asynchronous circuits have also been proposed [37], with a translation of handshake protocols to Petri nets for formal verification. Such detailed models allow fine analyses of the timing behavior (using, e.g., model checking, refinement checking, reachability checking [38], theorem proving [39] [40], etc. ), so as to study the propagation of glitches [41] [42] or verify the correctness of speed-independent circuits [43]; however, the use of very detailed models often limits the size of circuit that can be analyzed.…”

Section: Related Workmentioning

confidence: 99%

Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

Bouzafour

Renaudin

Garavel

et al. 2018

2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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Asynchronous circuits have key advantages in terms of low energy consumption, robustness, and security. However, the absence of a global clock makes the design prone to deadlock, livelock, synchronization, and resource-sharing errors. Formal verification is thus essential for designing such circuits, but it is not widespread enough, as many hardware designers are not familiar with it and few verification tools can cope with asynchrony on complex designs. This paper suggests how an industrial design flow for asynchronous circuits, based upon the standard HDL SystemVerilog, can be supplemented with formal verification capabilities rooted in concurrency theory and modelchecking technology. We demonstrate the practicality of our approach on an industrial asynchronous circuit (4000 lines of SystemVerilog) implementing a memory protection unit.

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“…• Roncken et al [13] use go signals to control progress in asynchonrous circuits in a fine-grained manner for the purpose of silicon test and debug. The idea is further developed in [14], where go signals are used to model non-determinism in asynchonrous circuits in the context of formal verification of link-joint models using the theorem proving system ACL2. In this paper, the enable vector en plays the same role as go signals but at the level of individual gates instead of link-joint components.…”

Section: B Related Workmentioning

confidence: 99%

Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools

Tarawneh

Mokhov

2018

2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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Asynchronous circuits are pervasive in modern synchronous systems, but they are still designed and verified in isolation, using dedicated asynchronous design flows, formalisms and tools. We describe a method to verify gate-level asynchronous circuit implementations using formal verification tools and property languages for synchronous logic. We report observations and findings from applying this method to use case designs using an industrial and an open source formal verification tools for synchronous logic (Cadence Incisive Formal and Xprova), and compare performance and verification capabilities against two verification tools for asynchronous circuits. Finally, we discuss the advantages and practical considerations of bridging synchronous logic verification tools to the domain of asynchronous circuits. Our main conclusion is that, while there are performance penalties, there is still significant value in enabling users to verify asynchronous circuits using tools that may be more familiar, trusted or more widely adopted.

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A Framework for Asynchronous Circuit Modeling and Verification in ACL2

Cited by 6 publications

References 10 publications

A Security Analysis of Circuit Clock Obfuscation

A Security Analysis of Circuit Clock Obfuscation

Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools

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