Timing Verification and the Timing Analysis Program

Abstract

Timing Verification consists of validating the path delays (primary input or storage element to primary output or storage element) to be sure they are not too long or too short and checking the clock pulses to be sure they are not too wide or too narrow. The programs addressing these problems neither produce input patterns like test pattern generators nor require input patterns like traditional simulators. Timing Analysis, a program described recently in [HI82a], is designed to analyze the timing of large digital computers and is based, in part, on the concepts disclosed in a patented method [DO81] for determining the extreme characteristics of logic block diagrams. The output of Timing Analysis includes "slack" at each block to provide a measure of the severity of the timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach.

Delay optimization of linear depth boolean circuits with prescribed input arrival times

“…At one of the final stages in the design process of a chip, the tool that performs the so-called static timing analysis [2][3][4] detects paths of 'negative slack'. These are paths on which the propagation of the signal is too slow to guarantee the correct functioning of the chip.…”

“…Our main result is a cubic-time dynamic programming algorithm that produces a circuit for functions f as in (1) whose delay is at most about 1.44 times the value of the lower bound (2). We describe this algorithm first for the function f 0 :…”

Maximization of power dissipation in large CMOS circuits considering spurious transitions

“…2) A three-valued logic (0, 1, or ) which denotes the value at the output of the gate during a time interval beginning at the start time of the element, and ending at the start time of the next element. We apply static timing analysis [11], [14] to create the sequences for a given circuit. The function, SEQUENCE(), implementing the procedure is shown below.…”

“…The estimation process is separated into two phases. In Phase I, we apply static timing analysis [11], [14] to find the time instants at which the gates can switch. The information obtained is then used in Phase II, in which the energy dissipated in a clock cycle is maximized based on an automatic test generation (ATG) technique.…”

A new accurate and hierarchical timing analysis approach

“…E f f d ive methods were proposed to block (e.g. [3]) level instead of circuit eve1 (e.g. However, constraining timing analysis tools to 1066-1400/93 $03.00 @ 1993 lEEE reduce the delay error margins, but their time complexity grows more rapidly than a linear function of the circuit size (as summarized in [6] .…”