A new accurate and hierarchical timing analysis approach

Abstract

A n~w and cficicnt procedure is proposed to evaluate the timing performance of VLSI circuits with rzrcuit level accuracy. The efficiency is obtained by rapidly identifying the crilical portions of the circuit al high hierarchical levels with rough delay modcls. These portions are then successively studied at i7ior-e detailed lcvels for inaxzinal accuracy. This procedure, itiipleinented and applied to several circuits, is shown to stgnificanily reduce the analysis time.