Taking advantage of high level functional information to refine timing analysis and timing information

Safinia, C.; Leveugle, Régis; Saucier, G.

doi:10.1109/edtc.1994.326853

Cited by 2 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Markov chain model based metrics for evaluating the performance of schedules was suggested in [3]. Several clock period estimation techniques have also been developed [4,5,6,7,8] for ASIC implementations. Static performance analysis techniques for software implementation on processors have been proposed in [9,10].…”

Section: Introductionmentioning

confidence: 99%

“…The clock period estimation of an implementation is not affected whether the system is described and implemented as a single process or as a set of multiple communicating processes; hence, the clock period estimation techniques described above [4,5,6,7,8] are applicable to such multi-process systems. However, applying existing performance analysis techniques to estimate number of clock cycles [1,2,9] of systems described as concurrent communicating processes will lead to inaccurate results.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Performance analysis of a system of communicating processes

Dey¹,

Bommu²

1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

View full text Add to dashboard Cite

Efficient exploration of the system design space necessitates fast and accurate performance estimation as opposed to the computationally prohibitive alternative of exhaustive simulation. This paper addresses the issue of worst-case performance analysis of a system described as a set of concurrent communicating processes. We show that the synchronization overhead associated with inter-process communication can contribute significantly to the overall system performance. Application of existing performance analysis techniques, which target single process descriptions, lead to inaccurate performance estimates as the synchronization overhead is not accounted for. We present PERC, a fast and accurate worst-case performance analysis technique which analyzes inter-process communication, and accounts for synchronization overhead while computing the worst-case performance estimate of a given system implementation. Application of PERC to example systems described as multiple communicating processes shows the ability of the proposed method to accurately estimate the worst-case performance of the system implementation.I. INTRODUCTION Increasing complexity, aggressive design requirements, and shorter product cycles are necessitating fast and efficient exploration of the system design space, requiring the capability of analyzing the system performance, power, and other design metrics for several system implementations at high levels of abstraction. This paper introduces a technique to estimate the worst-case performance of a system described as a set of concurrent communicating processes. The performance of a system is determined by both the number of clock cycles required by the system implementation, as well as the clock period of the implementation. A possible way of evaluating the worst case system performance is by exhaustive simulation of the system implementation. However, the approach can be computationally inhibitive, especially in an iterative design framework, where at every iteration, multiple implementation alternatives need to be evaluated. Hence the need for fast static performance analysis and estimation tools. Several performance analysis and delay estimation techniques have been developed recently. In [1,2], analysis techniques were developed to compute the average number of clock cycles required by a scheduled implementation of a behavioral description. Markov chain model based metrics for evaluating the performance of schedules was suggested in [3]. Several clock period estimation techniques have also been developed [4,5,6,7,8] for ASIC implementations. Static performance analysis techniques for software implementation on processors have been proposed in [9,10].

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance analysis of a system of communicating processes

Dey¹,

Bommu²

1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

View full text Add to dashboard Cite

show abstract

Fast true delay estimation during high level synthesis

Bhattacharya¹,

Dey²,

Brglez

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

This paper addresses the problem of true delay estimation during high level design. The true delay is the delay of the longest sensitizable path in the resulting circuit, as opposed to the topological delay which is the delay of the longest path in the circuit. The existing delay estimation techniques either estimate the topological delay, which may be pessimistic if the longest path is unsensitizable or false, or estimate the true delay using gate-level timing analysis which may be prohibitively expensive. Resource sharing in high level synthesis can create false paths in the circuit implementation. Hence, determining the clock period using topological delay can be unduly conservative, resulting in excessive hardware to meet tight timing speci cations. In this paper, we introduce an e cient technique to compute an estimate of the true delay. The proposed technique relies on partitioning the paths in the circuit and topological delay computation, and not on path sensitization. The paths in the implementation are partitioned into two sets given the high level information on scheduling and resource sharing: the complete determining path set or CDP R , and the non-determining path set or NDP R. We prove that the delay of the longest path in CDP R is lower bounded by the true delay and upper bounded by the topological delay of the circuit. Consequently, an estimate of the true delay of the resulting circuit can be computed by measuring the topological delay of the longest path in CDP R. We have developed a Functional delay ESTimation tool FEST. Experimental results on a set of benchmarks reveal the following: about 50% of all paths are in NDP R and can be ignored for true delay estimation, and the true delay estimates are on the average 15% less than the topological delay. The high level true delay estimates are accurate, as veri ed by comparing with the true delays obtained by gate-level timing analysis on actual implementations. Furthermore, results reveal that high level true delay estimation can be done very fast, even when gate-level true delay estimation becomes infeasible.

show abstract

Taking advantage of high level functional information to refine timing analysis and timing information

Cited by 2 publications

References 11 publications

Performance analysis of a system of communicating processes

Performance analysis of a system of communicating processes

Fast true delay estimation during high level synthesis

Contact Info

Product

Resources

About