Efficient exploration of the system design space necessitates fast and accurate performance estimation as opposed to the computationally prohibitive alternative of exhaustive simulation. This paper addresses the issue of worst-case performance analysis of a system described as a set of concurrent communicating processes. We show that the synchronization overhead associated with inter-process communication can contribute significantly to the overall system performance. Application of existing performance analysis techniques, which target single process descriptions, lead to inaccurate performance estimates as the synchronization overhead is not accounted for. We present PERC, a fast and accurate worst-case performance analysis technique which analyzes inter-process communication, and accounts for synchronization overhead while computing the worst-case performance estimate of a given system implementation. Application of PERC to example systems described as multiple communicating processes shows the ability of the proposed method to accurately estimate the worst-case performance of the system implementation.I. INTRODUCTION Increasing complexity, aggressive design requirements, and shorter product cycles are necessitating fast and efficient exploration of the system design space, requiring the capability of analyzing the system performance, power, and other design metrics for several system implementations at high levels of abstraction. This paper introduces a technique to estimate the worst-case performance of a system described as a set of concurrent communicating processes. The performance of a system is determined by both the number of clock cycles required by the system implementation, as well as the clock period of the implementation. A possible way of evaluating the worst case system performance is by exhaustive simulation of the system implementation. However, the approach can be computationally inhibitive, especially in an iterative design framework, where at every iteration, multiple implementation alternatives need to be evaluated. Hence the need for fast static performance analysis and estimation tools. Several performance analysis and delay estimation techniques have been developed recently. In [1,2], analysis techniques were developed to compute the average number of clock cycles required by a scheduled implementation of a behavioral description. Markov chain model based metrics for evaluating the performance of schedules was suggested in [3]. Several clock period estimation techniques have also been developed [4,5,6,7,8] for ASIC implementations. Static performance analysis techniques for software implementation on processors have been proposed in [9,10].
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
customersupport@researchsolutions.com
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.