Delay optimization of linear depth boolean circuits with prescribed input arrival times

Abstract

We consider boolean circuits C over the basis Ω = {∨, ∧} with inputs x

Fast Prefix Adders for Non-uniform Input Arrival Times

“…We will use the delay properties of the prefix operator (2) aiming to minimize the delay of logic circuits for additions instead of the corresponding prefix graphs. This idea was used by [8], who proposed a cubic-time dynamic programming algorithm to compute a fast carry bit circuit.…”

“…Adder 2W + 6 log 2 log 2 n + O(1) 6n log 2 log 2 n √ n + 1 O(n 2 ) / O(n 2 log n) Here Adder 1.441W + 5 log 2 log 2 n + 4.5 6n log 2 log 2 n √ n + 1 O(n log n) / O(n log 2 n) Table 1: Improvements over [8,9], where W = log 2 n i=1 2 t i is a lower bound for the delay. Running times assume constant/linear time for binary addition.…”

“…For a single carry bit computation with arrival times, Rautenbach et al [8] give a dynamic programming algorithm with cubic running time. The algorithm restructures an And-Or-path similar to a prefix tree.…”

“…2 . We first prove a similar delay bound to [8], but instead of bounding the recursive function D, we explicitly construct our solution and obtain useful structural information about it. Lemma 2.4.…”

BonnTools: Mathematical Innovation for Layout and Timing Closure of Systems on a Chip

“…To overcome the limitations of purely local and conservative changes, we have developed a totally novel approach that allows for the redesign of the logic on an entire critical path taking all timing and placement information into account [35]. Whereas most procedures for Boolean optimization of combinational logic are either purely heuristic or rely on exhaustive enumeration and are thus very time consuming, our approach is much more effective.…”