The delay of circuits whose inputs have specified arrival times

Delay optimization of linear depth boolean circuits with prescribed input arrival times

“…As a consequence, we can construct circuits over the basis {∨, ∧, ¬} for the addition of two binary n-digit numbers whose delay is at most 1.44 times the optimal delay plus some small constant. Unfortunately, the number of gates of these circuits is quadratic in n. In [8] we describe circuits for the same task whose delay is essentially at most twice the lower bound and whose size is O(n log(log(n))).…”

“…x i , then a tree as considered in the above proof immediately leads to a circuit for f of minimum delay and can obviously be constructed in polynomial time (see [8]). …”

“…The delay delay(C) of C is defined as the maximum delay of an input in C. Given a function f and arrival times as above, we denote the minimum delay of a circuit for f by delay(f ). For some first and fundamental results on this notion of delay we refer the reader to [8].…”

“…Our algorithm allows the construction of an adder for two n-bit binary numbers which is also of quadratic size but provably has at most about 1.44 times the minimum delay. In [8] we describe circuits for the prefix problem taking arrival times into account which immediately leads to adders for two n-bit binary numbers which are of size O(n log(log(n))) and have at most about twice the minimum delay.…”

BonnTools: Mathematical Innovation for Layout and Timing Closure of Systems on a Chip

“…Besides the described procedure for logic optimization on critical paths we have developed theoretical machinery for designing complex subfunctions taking timing information into account [36].…”