Timing analysis of scan design integrated circuits using stimulation by an infrared diode laser in externally triggered pulsing condition

Kiyan, Tüba; Brillert, Christof; Boit, Christian

doi:10.1016/j.microrel.2008.07.028

Cited by 5 publications

(2 citation statements)

References 15 publications

(13 reference statements)

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“…Firstly, ATE running the scan chain integrity test (also known as scan chain check test) in a loop manner, LADA technique is then applied on a good die to reveal the locations of scan cells as the laser rasters across the region of interest. Such LADA based phenomenon is also discussed by Kiyan et al [6]. In this way, any knowledge on scan chain design information is not required.…”

Section: Scan Cell Localization By Ladamentioning

confidence: 85%

A non destructive scan diagnosis based fault isolation technique verification method using infrared laser stimulation on wafer level

You

Goh

Yeoh

et al. 2013

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Scan diagnosis based fault isolation technique using Electronic Design Automation (EDA) software tool is highly effective and commonly adopted for product chain and logic yield learning. For every new device introduction, prior to implementation of scan diagnosis for yield ramp, it is necessary to validate the success and accuracy of the test patterns generated for diagnosis. The accuracy of the fail suspects isolated is typically verified on physical failure analysis (PFA). In this paper, a non destructive verification methodology without the need for design information, die packaging and physical failure analysis is proposed. The contribution is a faster turnaround time for success qualification. The experimental data in this work demonstrates the feasibility and presents an added application for wafer level laser diagnostics.

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Section: Scan Cell Localization By Ladamentioning

confidence: 85%

A non destructive scan diagnosis based fault isolation technique verification method using infrared laser stimulation on wafer level

You

Goh

Yeoh

et al. 2013

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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show abstract

“…The overall potential of this approach is by far not exhausted yet. More specific applications are expected that increase precision, like pulsed lasers [16] and phase sensitive approaches.…”

Section: 2: Laser Stimulation / Laser Voltage Probingmentioning

confidence: 99%

Scale, function and materials: debug and diagnosis in electronic device technology roadmap

Boit

2008

2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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Debug and Diagnosis of Integrated Circuits with physical techniques is necessarily correlated strongly to the innovation of electronic device technology. Miniaturization and scaling were main reasons for the introduction of signal access through chip backside in recent years. The introduction of new materials is adding critical challenges, even on the active device level. Based on the technology roadmap to 32nm and below, this article presents the boundary conditions for functional device analysis and discusses the analysis options. The potential of established techniques is assessed with respect to the mismatch of optical resolution and nanoscale device dimensions, to the resolution gain of scanning probe techniques vs. working distance requirements, to the FIB techniques for circuit edit and ultra thin silicon preparation. Applications of innovative approaches are demonstrated, and critical issues like thermal / mechanical management are discussed.

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Backside failure analysis techniques: What's the gain of silicon getting thinner?

Boit¹,

Schäfer

Abou‐Ras

et al. 2014

Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Timing analysis of scan design integrated circuits using stimulation by an infrared diode laser in externally triggered pulsing condition

Cited by 5 publications

References 15 publications

A non destructive scan diagnosis based fault isolation technique verification method using infrared laser stimulation on wafer level

A non destructive scan diagnosis based fault isolation technique verification method using infrared laser stimulation on wafer level

Scale, function and materials: debug and diagnosis in electronic device technology roadmap

Backside failure analysis techniques: What's the gain of silicon getting thinner?

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