Frequency mapping methodology is an effective diagnostic tool for detection of manufacturing defects in scan chains. It analyses reflected laser modulations from toggling scan cells to localize defective scan path or scan cell. In this paper, we demonstrate experimentally that the use of solid immersion lens technology to enhance signal and spatial resolution is not a prerequisite for this technique up till 28 nm technology node. We present case studies to show the effectiveness of frequency mapping for detecting systematic and random broken scan chain failures on a 28 nm technology node test chip. We achieved 81% success rate in this methodology.
This paper proposes a novel floating high-voltage level shifter (FHV-LS) with the pre-storage technique for high speed and low deviation in propagation delay. With this technology, the transmission paths from input to output are optimized, and thus the propagation delay of the proposed FHV-LS is reduced to as low as the sub-nanosecond scale. To further reduce the propagation delay, a pull-up network with regulated strength is introduced to reduce the fall time, which is a crucial part of the propagation delay. In addition, a pseudosymmetrical input pair is used to improve the symmetry of FHV-LS structurally to balance between the rising and falling propagation delays. Moreover, a start-up circuit is developed to initialize the output state of FHV-LS during the VDDH power up. The proposed FHV-LS is implemented using 0.3-µm HVCMOS technology. Post-layout simulation shows that the propagation delays and energy per transition of the proposed FHV-LS are 384 ps and 77.7 pJ @VH = 5 V, respectively. Finally, the 500-points Monte Carlo are performed to verify the performance and the stability.
Conventional software scan diagnosis using Electronic Design Automation (EDA) tools and hardware diagnosis using frequency mapping technique, are established methodologies for broken scan chains fault isolation. This work proposes a diagnostic workflow that integrates both methodologies to enhance accuracy and reduce turnaround time for debug. Experimental results are presented to demonstrate the effectiveness of this workflow for systematic fail dies analysis.
Pulsed-LADA is found to play an important role in the advancement of next-generation LADA and it is reported that tens of μs pulses with 10 kHz frequency is sufficient to observe enhancements in carrier injection. Electrically-enhanced LADA (EeLADA), based on pulsed-LADA, is introduced as a new fault localization method capable to overcome current limitation of Laser Assisted Device Alteration (LADA) application on soft failure and extends it to hard failure debug. We present the EeLADA methodology and experimental data to demonstrate its feasibility.
A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.
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