Scale, function and materials: debug and diagnosis in electronic device technology roadmap

Abstract

Debug and Diagnosis of Integrated Circuits with physical techniques is necessarily correlated strongly to the innovation of electronic device technology. Miniaturization and scaling were main reasons for the introduction of signal access through chip backside in recent years. The introduction of new materials is adding critical challenges, even on the active device level. Based on the technology roadmap to 32nm and below, this article presents the boundary conditions for functional device analysis and discusses the analysis options. The potential of established techniques is assessed with respect to the mismatch of optical resolution and nanoscale device dimensions, to the resolution gain of scanning probe techniques vs. working distance requirements, to the FIB techniques for circuit edit and ultra thin silicon preparation. Applications of innovative approaches are demonstrated, and critical issues like thermal / mechanical management are discussed.