Time-Interleaved $\Sigma\Delta$ Modulators for FPGAs

Abstract

This paper describes and analyzes a technique of increasing a sampling rate in a Σ∆ modulator based on a discrete time description, which is an extension of existing techniques of parallelization. The limitations in signal to noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of LP Σ∆ modulator characterized by short critical path is used in this paper to validate the technique.An implementation of a modulator shows the increase in the sampling rate from 100 M Hz to 400 M Hz.

Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI

“…A comparison between these 2 methods is made in [7] in terms of hardware requirements for a L th order M-channel DSM (Table I), showing a highly reduced complexity especially when increasing the number of channels. Nevertheless, this method has been used only recently in a 4channel TI DSM implementation on FPGA working at a maximum sampling frequency of 400 MHz with a narrow signal bandwidth of 1.25 MHz [8].…”

Time‐interleaving design of error‐feedback sigma‐delta modulators with infinite impulse response noise transfer function

“…In order to gain speed, different techniques for the decomposition of arbitrary-order IIR transfer functions have been proposed [7][8][9][10][11][12][13][14][15]. Time-interleaving (TI) has been used to overcome or alleviate speed constraints in the implementation of SDMs [9][10][11][12]. The modulator of Figure 1, clocked at the sampling frequency f s , is decomposed in N parallel paths clocked at the low rate f s /N, by means of the filter bank HðzÞ shown in Figure 2 [10].…”

“…In order to gain speed, different techniques for the decomposition of arbitrary-order IIR transfer functions have been proposed [7][8][9][10][11][12][13][14][15]. Time-interleaving (TI) has been used to overcome or alleviate speed constraints in the implementation of SDMs [9][10][11][12].…”

Analysis of 3-Level Bandpass Sigma-Delta Modulators With 2-Level Output

“…This is because high oversampling ratio used in both M enables sampling the input signal at a fraction of f . A zero-insertion or sample-hold techniques [4], [5] can be used to reduce power consumption of the linearization by factor of 4, 8, or more.…”

“…This technique can be suitable in alldigital transceivers [6], where reduction of quantization noise power is of importance. It can be also used to further enhance SNR in the time-interleaved modulators [4].…”