This paper describes and analyzes a technique of increasing a sampling rate in a Σ∆ modulator based on a discrete time description, which is an extension of existing techniques of parallelization. The limitations in signal to noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of LP Σ∆ modulator characterized by short critical path is used in this paper to validate the technique.An implementation of a modulator shows the increase in the sampling rate from 100 M Hz to 400 M Hz.
Abstract-A ΣΔ-driven RF switch-mode power amplifier is inherently linear only when it has a two-level output. At the same time, a two-level output generates the largest amount of quantization noise. This brief analyzes the effect of nonequal level spacing in a three-level ΣΔ output and provides a method for shaping the corresponding error noise to regions outside the band of interest. Subsequently, the nonlinearity-shaping property is utilized to obtain an improved two-level drive signal based on three-level ΣΔ modulation. The new binary drive signal is proven to have better adjacent channel leakage ratio and higher coding efficiency than a conventional two-level ΣΔ modulator. In the investigated case, measured coding efficiency improves from 8.9% of the conventional two-level modulator to 21% of the modified two-level modulator.Index Terms-Coding efficiency, sigma delta, switch-mode power amplifier (SMPA).
Abstract-When a delta-sigma modulator (DSM) is placed before a class D switching stage the combination can be used to amplify time varying envelope signals. However a bandpass DSM is commonly employed and is required to have a sampling frequency approximately four times the carrier frequency. At RF or microwave frequencies proprietary hardware was previously needed to implement the DSM. However, it is shown here in simulation and from experimental measurement that a suitable DSM for class S power amplifiers can be implemented at RF and microwave frequencies using mid-range FPGA technology.
In this paper a platform that implements the digital processing and RF carrier generation for class S PA operation is presented. This implementation consists of a bandpass delta sigma modulator (DSM) with a multi-level quantizer followed by a pulse width modulator and frequency upconversion stage. The principle of operation is described and validation is provided through simulation and experimental measurements on a prototype of the modulator. It is shown that the output from the new modulator can achieve significant improvements in SNR performance compared to a two level DSM with little added computational overhead.
-This paper presents an end-to-end high frequency class S power amplifier. A description of the full testbench and some important points on generation of RF outputs from FPGA devices and current mode class D design are given. Experimental measurements are provided for the prototype PA consisting of a signal generator, analog to digital converter, driver circuit, current mode class D switching stage and bandpass filter. Theory and experimentally measured results for this prototype are presented for a multi tone signal centred at 930 MHz and with a total output power of 24.7dBm.
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