Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI

Marin, Razvan-Cristian; Frappé, Antoine; Cathelin, Andreia

doi:10.1109/newcas.2015.7182049

Cited by 8 publications

(8 citation statements)

References 11 publications

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“…3, where the STF, NTF and the associated pole-zero plots are shown for four different custom zeros, namely z1 = 0.25+0.97j, z2 = 0.75+0.66j, z3 = 0.75-0.66j, z4 = 0.25-0.97j. First of all, we notice that the STF is the same for all the cases, as indicated in (7). Secondly, the sign of the imaginary part determines the position of the custom zero, namely if Im(z) > 0, then the normalized frequency is fz > 0.…”

Section: B Proposed 1 St Order Cdsmmentioning

confidence: 79%

“…In order to target advanced communication standards, [7] presents the design of a single-bit Delta-Sigma Modulator as part of a digital transmitter, focusing on time-interleaving to enable high-speed applications (up to 6 GS/s sample rate) and large signal bandwidths (up to 160 MHz).…”

Section: A Out-of-band Noise Vs Multi-standard Coexistencementioning

confidence: 99%

“…Following the proposed CDSM design method, the first step is to define the specific SNR requirements for the targeted application, which determine the order of the CDSM. For instance, [7] describes the design of a 3 rd order DSM targeting signal bandwidths from 20 MHz up to 160 MHz with an SNR larger than 67 dB.…”

Section: Applicationmentioning

confidence: 99%

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Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

Marin

Frappé

2018

IEEE Trans. Circuits Syst. I

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This paper presents a Complex Delta-Sigma Modulator (CDSM) designed for the integration in a digital transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a Delta-Sigma Modulator (DSM) has the advantage of increased performances in terms of signal-tonoise-ratio (SNR) in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the succeeding filtering stage. These constraints could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross-coupling the In-phase (I) and Quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross-couplings from the I and Q quantizers' outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30 dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient fine/coarse configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta Sigma Modulator (DSM), Complex Delta Sigma Modulator (CDSM), finite impulse response (FIR), multistandard coexistence, digital transmitter; I. INTRODUCTION ECENT progress in advanced CMOS integrated digital transmitter (TX) architectures [1] [2] has been focusing on reducing the power consumption and circuit area to follow the trend of increased data rates and signal bandwidths (BW) in communication standards, e.g. IEEE 802.11 standard.

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Section: B Proposed 1 St Order Cdsmmentioning

confidence: 79%

Section: A Out-of-band Noise Vs Multi-standard Coexistencementioning

confidence: 99%

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Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

Marin

Frappé

2018

IEEE Trans. Circuits Syst. I

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“…In this case, one out of two values in the I and Q paths can be dropped. Thus, the mixer is reduced to time-interleaving the appropriate [15].…”

Section: Theory Of Operationmentioning

confidence: 99%

Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

Marin¹,

Frappé²,

Stefanelli³

et al. 2019

IEEE Trans. Microwave Theory Techn.

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This paper presents a single-bit RF transmitter based on single-bit switched-capacitor RF digital-to-analog converters (DAC) embedded in an FIR filter (FIR-DAC). The transmitter system comprises a single-bit quadrature Delta-Sigma Modulator (ΔΣM), a digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete and continuous time filtering. The onchip part of the FIR-DAC is built exclusively with CMOS inverters and Metal-Oxide-Metal (MOM) capacitors, which are implemented in the interconnect layers to propose a compact fully-digital solution, suitable for advanced CMOS nodes.A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete and continuous-time filtering, the out-ofband quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in 28nm FD-SOI CMOS technology with 10 metal layers and occupies a total active area of only 0.047 mm 2 . The overall power consumption is 38 mW at 4.6 dBm peak output power, 900 MHz carrier frequency and 1 V supply. FD-SOI body-bias Vt tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise highfrequency I/Q interleaving, which enables high image and local oscillator (LO) rejections. The resulting power consumption, surface and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications.

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“…While band-pass delta-sigma modulators are feasible, the more common approach is to use low-pass modulators in an I-Q architecture combined with a digital mixer to reach a RF band located at ¼ of the sampling frequency [1]. This approach allows to lower the sampling frequencies of the delta-sigma modulators to fs/2, and also permits time-interleaved implementations further lowering the effective sampling frequency of the digital modulators [2]. Only a small portion of the systems operates at the actual sampling frequency.…”

Section: Delta-sigma Modulator Based Digital Transmittersmentioning

confidence: 99%

Digital RF transmitter architectures exploiting FIRDACs in various configurations

Frappé

2017

2017 IEEE 12th International Conference on ASIC (ASICON)

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HAL is a multidisciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI

Cited by 8 publications

References 11 publications

Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

Digital RF transmitter architectures exploiting FIRDACs in various configurations

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