Time‐Efficient Stateful Dual‐Bit‐Memristor Logic

Abstract

Stateful logic provides an attractive device‐level solution in achieving in‐memory computation, which can solve the critical problem of the von Neumann bottleneck − “memory wall” − in the current computer architecture. Recently, fully functional stateful logic operations and cascading are reported using a TiOx‐based dual‐bit memristor. In that work, all the 16 Boolean logic functions are accomplished in a stateful dual‐bit memristor, which can be expanded to more complicated computational tasks. This logic scheme is much more compact compared with the current complementary semiconductor field effect transistors based logic, providing the system with great area efficiency as well as energy‐saving performance. In such stateful logic device, the logic flow (cascading) is made along the time dimension. Therefore, “time efficiency” is the critical factor for estimating its performance. In this paper, two methods, changing the logic coding scheme and configuring the parallel‐circuit morphology, are suggested to improve the time efficiency of the previous dual‐bit memristor‐based logic. By implementing the two methods, a full adder can be demonstrated with three dual‐bit memristors and 12 operation steps, which corresponds to a 55.6% improvement compared with the previous work.

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

“…Figure 5c shows the comparison of the efficiency and practical feasibility of various stateful logic technologies for executing a one-bit full adder. [5,7,15,31,32,[46][47][48] It shows the gate used, the number of cells involved, and the number of steps required to execute the one-bit full adder in each study. Here, to compare the computing efficiency, we introduce a total efficiency cost value, which is a multiplication of the number of cells (spatial cost) and the number of steps (temporal cost).…”

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

“…According to the available stable resistance states, RRAM can be categorized into two types: analog RRAM denotes those devices whose resistances can be programmed to any value between the highest resistance state (HRS) and the lowest resistance state (LRS), whereas binary RRAM behaves as a normal memory device with a stable HRS and LRS. [48][49][50][51][52][53][54] Binary inputs are stored into RRAM devices as the resistance (conductance) before performing computation. As early as in 2009, a 1 kb RRAM array in a one-transistor-one-RRAM (1T1R) cell structure was successfully integrated with CMOS read/write circuits.…”

“…As early as in 2009, a 1 kb RRAM array in a one-transistor-one-RRAM (1T1R) cell structure was successfully integrated with CMOS read/write circuits. [50] A large-scale array of stateful logical RRAM is the aggregation of these basic logic gates similar to the transistor-based arithmetic units. These devices achieved four separated resistance levels.…”

A forming-free ReRAM cell with low operating voltage

“…In the coming era of the Internet of Things (IoT) and big data, as the most promising successor of the next-generation non-volatile memory [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15], ReRAM still meets some practical problems that need to be solved. First, in most cases, an electro-forming process is a prerequisite for the repeatable resistive switching, in which a large voltage is applied to the pristinely insulating ReRAM device to generate sufficient oxygen vacancy defects or metal ions to construct a conducting path.…”