Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

Jefremow, Mihail; Kern, Thomas; Allers, W.; Peters, Christian; Otterstedt, J.; Bahlous, O.; Hofmann, K.R.; Allinger, R.; Kassenetter, S.; Schmitt‐Landsiedel, D.

doi:10.1109/isscc.2013.6487706

Cited by 39 publications

(22 citation statements)

References 4 publications

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“…The current sensing margin ( ) cannot be increased with a relaxed sensing time ( ), necessitating the use of small current-offset ( ) CSAs for NVMs or ReRAMs. Previous current-sampling based CSAs [25], [26] achieved a small but were not operable at a low because of the large voltage headroom requirement. A body-drain driven (BDD) CSA [16] was proposed to achieve near-0.5 V operations; however, a high yield from the small R-ratio could not be achieved at a low , preventing the use of CSAs for low-applications.…”

Section: B Challenges Of Low-voltage Sensing For Resistive Rammentioning

confidence: 99%

Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Chang

Chien

et al. 2015

IEEE J. Solid-State Circuits

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The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-, and slow read access time ( ) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current ( ) resulting from the wide distribution of write (SET)-times ( ). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately greater sensing margin for lower and a faster read speed across a wide range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed tocut off the of devices with a rapid . The SBWT scheme reduces 99 of the with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved 404 ns when 0.27 V and confirmed the cutoff by the SBWT.Index Terms-ReRAM, RRAM, sense amplifier, voltage-mode sense amplifier, write driver. 0018-9200

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Section: B Challenges Of Low-voltage Sensing For Resistive Rammentioning

confidence: 99%

Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Chang

Chien

et al. 2015

IEEE J. Solid-State Circuits

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“…Table I shows the comparison between the SDSC with DSTA-VLSA, with OC-VLSA, and LOC-SA. Additionally, an OCTS-SC [20] and TDSC [21], which cancel the offset voltage of sensing circuit instead of latch sense amplifier, are compared. We note that OCTS-SC and TDSC use the DSTA-VLSA as latch sense amplifier.…”

Section: Cmentioning

confidence: 99%

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

Song

Kim

et al. 2015

IEEE Trans. Circuits Syst. I

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As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2 faster sensing speed, 1.12 lower read energy, and 1.13 smaller area when compared with the best value of design parameters of other sense amplifiers.Index Terms-Latch sense amplifier, MRAM, offset cancellation technique, read access pass yield, STT-RAM.

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“…However, conventional CSAs are incapable of achieving low-VDD sensing for the reduced SM and the degraded sensing speed. Time-Differential SA (TDSC-SA) and Split-Path SA (SP-SA) are proposed to double the SM [10,11,12], however, they suffer from longer sensing time. Body biasing technique (BB-SA) has been introduced to provide faster sensing and to alleviate the limitation in VDD [13,14], but the enhancement is finitely.…”

Section: Introductionmentioning

confidence: 99%

A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique

Yin

Dou

Dong

et al. 2019

IEICE Electron. Express

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There are two major challenges in developing the sensing circuit for ReRAM in deep submicron technologies, including: 1) the reduced sensing margin (SM) due to the lowered supply voltage (VDD). 2) the degraded read access pass yield caused by the increased processvoltage-temperature (PVT) variations. A Reference Clamping Sense Amplifier (RC-CSA) with Amplifier Assisted load PMOS and Dynamic Precharge circuit is proposed to deal with these two challenges. Simulation results show that the RC-CSA is able to provide over 200 mV SM with VDD down to 0.55 V, and capable to work with a large bit-line loading (4096 cells per BL). The typical read yield is 99.9% for 32-Mb macro with sensing time of 4.6 ns under 0.75 V VDD. Overall, RC-CSA is very suitable for low-VDD and high-density applications.

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Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

Cited by 39 publications

References 4 publications

Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique

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