Time Difference Amplifier with Robust Gain Using Closed-Loop Control

As the scaling of LSI is going to extremely fine regions toward the ultimate feature size, one of difficulties faced in analog circuit design is reduction of the dynamic range (DR) due to the supply voltage reduction. Unlike digital circuits, where the noise margin for logic operation is the key criterion, analog circuits need an enough DR. The reduced supply voltage directly results in DR degradation of the conventional analog circuits in the voltage-domain. Especially in mixed-signal LSIs, supply voltage instability, caused by logic operation, tends to degrade DR further. In this paper, we will first discuss potential capability of a new paradigm of time-domain circuits by comparing with the conventional voltage/current-domain circuits in terms of DR and power consumption. Next, as basic circuit components for the time-domain approach, current status of TDA (Time-Difference Amplifier) and TDC (Time-to-Digital Converter) will be reviewed. Finally, some application examples of the time-domain circuits are introduced to demonstrate the feasibility of the time-domain approach.

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“…Another TDA, which is robust against PVT variation using a delay-ratio lock loop [6], is shown in Fig. 5.…”

Section: Time Difference Amplifiersmentioning

confidence: 99%

Time-domain approach for analog circuits in deep sub-micron LSI

Asada

Nakura²,

Iizuka

et al. 2018

IEICE Electron. Express

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“…The AND gate is for a power gating to stop the oscillation of the VCO just after the 1st conversion to reduce power consumption. Figure 1(b) shows the basic structure of the TDA [18], the variable delay cells and the bias generator. The delay of variable delay cells is controlled digitally by activating or deactivating transistors, M n and M p , so that the variable delay cells become fast or slow.…”

Section: A Tdc Structurementioning

confidence: 99%

A 128-channel, 9ps column-parallel two-stage TDC based on time difference amplification for time-resolved imaging

Mandai

Charbon

2011

2011 Proceedings of the ESSCIRC (ESSCIRC)

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Abstract-This paper proposes a 128-channel column-parallel two-stage time-to-digital converter (TDC) utilizing a time difference amplifier (TDA) and shows measurement results with a 0.35um CMOS process. The 1st stage operates as a coarse TDC, the time residue which is not converted in the 1st stage is amplified by a TDA, then converted by the 2nd stage TDC. As the gain of the time difference amplifier can be adjusted from 9 to 20, the time resolution of the TDC can be tuned from 20ps to 9ps. The time resolution variation due to PVT effects is ±12% without compensation, however calibration can be used to compensate for this variation.

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“…Time-domain signal processing is advantageous in that the signal expression is not limited to the supply voltage and in that most circuits can use digital circuits; therefore, it can enjoy the benefit of CMOS scaling. For example, the implementation of a time amplifier was discussed in [1] [2]. The time am-plifier with the gain of 4.8 was obtained using cross-coupled chains of variable delay cells.…”

Section: Introductionmentioning

confidence: 99%

A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer

Ohhata¹,

Hotta²,

Yamaguchi³

et al. 2017

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This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.

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Time Difference Amplifier with Robust Gain Using Closed-Loop Control

Cited by 25 publications

References 4 publications

Time-domain approach for analog circuits in deep sub-micron LSI

Time-domain approach for analog circuits in deep sub-micron LSI

A 128-channel, 9ps column-parallel two-stage TDC based on time difference amplification for time-resolved imaging

A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer

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