Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

Takahashi, H.; Minakata, H.; Morisaki, Yasuhiro; Xiao, Shiqin; Nakabayashi, Masaaki; Nishigaya, Keita; Sakoda, T.; Ikeda, K.; Morioka, Hiroshi; Tamura, N.; Kase, M.; Nara, Yasuo

doi:10.1109/iedm.2009.5424332

Cited by 5 publications

(5 citation statements)

References 9 publications

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“…[8][9][10][11] Capping layers have been introduced to tune the work function of n/p-type band edge behavior. 12,13) However, another idea has been proposed in parallel to the progress in gate stack patterning, i.e. gate-last process integration, 14,15) with the purpose of minimizing degradation of the HKMG stack due to exposure to a high thermal budget.…”

Section: Introductionmentioning

confidence: 99%

Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

Kumar¹,

divya²,

Lee³

et al. 2022

Jpn. J. Appl. Phys.

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High pressure annealing technique at 6 atm over a wide range of temperature (200-450˚C) was introduced as post metal annealing on high-k/metal gate metal-oxide-semiconductor capacitor. To verify the ability of HPA in improving interface trap density, leakage issue the other MOS capacitor with same structure was annealed by MWA for comparison. The electrical performance of the capacitors under different etching mechanism was analyzed and the difference in characteristics such as flat-band voltage shift, oxide trapped charge, interface state density and leakage current were compared. The results show that high pressure annealing process is more effective to minimize the oxide trapped charged at low temperature than by high power MWA at 3000W, and the reduction in leakage current density after high pressure anneal at low temperature corresponds to the reduction in charge traps. High pressure annealing demonstrates great potential as the post-metallization annealing process for the high-k/metal gate structure .

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Section: Introductionmentioning

confidence: 99%

Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

Kumar¹,

divya²,

Lee³

et al. 2022

Jpn. J. Appl. Phys.

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“…[6] It was reported that introducing lanthanide elements or their compounds into HfO 2 can make flatband voltage V fb negatively shift accompanied by an enhancement in the k value of HfO 2 . [7][8][9][10][11] It is mostly believed that interface dipoles at the high-k/SiO 2 interface play a dominant role in V fb modulation. Regarding the origin of the interface dipole, some models have been proposed, such as the electronegativity model and the oxygen areal density difference model.…”

Section: Introductionmentioning

confidence: 99%

Effects of charge and dipole on flatband voltage in an MOS device with a Gd-doped HfO₂dielectric

Han¹,

Wang²,

Yang³

et al. 2013

Chinese Phys. B

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Gd-doped HfO2 has drawn worldwide interest for its interesting features. It is considered to be a suitable material for N-type metal-oxide-semiconductor (MOS) devices due to a negative flatband voltage (Vfb) shift caused by the Gd doping. In this work, an anomalous positive shift was observed when Gd was doped into HfO2. The cause for such a phenomenon was systematically investigated by distinguishing the effects of different factors, such as Fermi level pinning (FLP), a dipole at the dielectric/SiO2 interface, fixed interfacial charge, and bulk charge, on Vfb. It was found that the FLP and interfacial dipole could make Vfb negatively shifted, which is in agreement with the conventional dipole theory. The increase in interfacial fixed charge resulting from Gd doping plays a major role in positive Vfb shift.

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“…1,8) Recently, capping layer insertion at the top/bottom of high-k layers has been identified as one of the solutions for V TH tuning. [9][10][11][12][13][14] In nMOS, the use of group IIA and IIIB oxides (e.g., La, Y, and Dy) enables both V TH shift and equivalent oxide thickness (EOT) scaling simultaneously, resulting in improved transistor performance. [9][10][11][12] In pMOS, however, the range of V TH modulation by Al and Ti insertion is insufficient for achieving low-V TH transistor operation.…”

Section: Introductionmentioning

confidence: 99%

“…[9][10][11][12] In pMOS, however, the range of V TH modulation by Al and Ti insertion is insufficient for achieving low-V TH transistor operation. 14) An alternative method of pMOS transistor V TH tuning is the use of an epitaxial SiGe channel structure. [15][16][17][18] V TH lowering by more than 300 meV, as well as hole mobility enhancement, has been observed.…”

Section: Introductionmentioning

confidence: 99%

Physical Mechanism of Threshold Voltage Modulation by Ge Channel Ion Implantation in the TiN/HfO₂ Gate Stack Systems

Tsuchiya¹,

Berliner²,

Iijima³

et al. 2011

Jpn. J. Appl. Phys.

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We extensively investigated the physical origin of the threshold voltage V TH modulation by the Ge channel ion implantation (I/I) in HfO 2 /TiN/ polycrystalline Si gate stack systems. The possible V TH modulation factors were carefully distinguished from each other by changing the channel dopant concentration and the thickness of the gate dielectric films. It was found that the changes in energy-band offset and dopant concentration in the channel region are minor factors of the V TH modulation. However, it was also found that ÁV TH is sensitive to the oxidation condition of the interfacial oxide layer; a longer oxidation induces a larger ÁV TH . From the X-ray spectroscopy, we found that a Ge pile-up at the interfacial layer/ channel interface occurs, and that the V TH modulation range correlates well with the amount of piled-up Ge.

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Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

Cited by 5 publications

References 9 publications

Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

Effects of charge and dipole on flatband voltage in an MOS device with a Gd-doped HfO₂dielectric

Physical Mechanism of Threshold Voltage Modulation by Ge Channel Ion Implantation in the TiN/HfO₂ Gate Stack Systems

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Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

Cited by 5 publications

References 9 publications

Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

Effects of charge and dipole on flatband voltage in an MOS device with a Gd-doped HfO2dielectric

Physical Mechanism of Threshold Voltage Modulation by Ge Channel Ion Implantation in the TiN/HfO2 Gate Stack Systems

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Product

Resources

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Effects of charge and dipole on flatband voltage in an MOS device with a Gd-doped HfO₂dielectric

Physical Mechanism of Threshold Voltage Modulation by Ge Channel Ion Implantation in the TiN/HfO₂ Gate Stack Systems