Throughput enhancement technique for MAPPER maskless lithography

Wieland, Marco; Derks, Henk; Gupta, H. M.; Peut, T. van de; Postma, F.M.; Veen, A. H. V. van; Zhang, Y.

doi:10.1117/12.849447

Cited by 14 publications

(6 citation statements)

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“…In the future, a new prototype instrument equipped with more in-situ characterization techniques including a nanomanipulator for electrical measurement and nanoprofilometer for thickness measurement of ice thin-films, will provide more thorough understanding and more striking applications of IL. Finally, IL is a scalable technology, thanks to the development of multi-e-beam technologies with over 600,000 parallel e-beams [36]. High throughput production of 3D nanodevices is possible by combining IL and multi-e-beam technology.…”

Section: Opportunities and Future Perspectivesmentioning

confidence: 99%

Ice lithography for 3D nanofabrication

2019

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Section: Opportunities and Future Perspectivesmentioning

confidence: 99%

Ice lithography for 3D nanofabrication

2019

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“…1,2 Some characteristics and general specifications that are relevant for this study are repeated in this section. 1,2 Some characteristics and general specifications that are relevant for this study are repeated in this section.…”

Section: Matrix Platform and Flx 1200 Toolmentioning

confidence: 99%

Demonstration of electronic design automation flow for massively parallel e-beam lithography

Brandt

Belledent

Tranquillin

et al. 2014

J. Micro/Nanolith. MEMS MOEMS

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For proximity effect correction in 5 keV e-beam lithography, three elementary building blocks exist: dose modulation, geometry (size) modulation, and background dose addition. Combinations of these three methods are quantitatively compared in terms of throughput impact and process window (PW). In addition, overexposure in combination with negative bias results in PW enhancement at the cost of throughput. In proximity effect correction by over exposure (PEC-OE), the entire layout is set to fixed dose and geometry sizes are adjusted. In PEC-dose to size (DTS) both dose and geometry sizes are locally optimized. In PEC-background (BG), a background is added to correct the long-range part of the point spread function. In single e-beam tools (Gaussian or Shaped-beam), throughput heavily depends on the number of shots. In raster scan tools such as MAPPER Lithography's FLX 1200 (MATRIX platform) this is not the case and instead of pattern density, the maximum local dose on the wafer is limiting throughput. The smallest considered half-pitch is 28 nm, which may be considered the 14-nm node for Metal-1 and the 10-nm node for the Via-1 layer, achieved in a single exposure with e-beam lithography. For typical 28-nm-hp Metal-1 layouts, it was shown that dose latitudes (size of process window) of around 10% are realizable with available PEC methods. For 28-nm-hp Via-1 layouts this is even higher at 14% and up. When the layouts do not reach the highest densities (up to 10∶1 in this study), PEC-BG and PEC-OE provide the capability to trade throughput for dose latitude. At the highest densities, PEC-DTS is required for proximity correction, as this method adjusts both geometry edges and doses and will reduce the dose at the densest areas. For 28-nm-hp lines critical dimension (CD), hole&dot (CD) and line ends (edge placement error), the data path errors are typically 0.9, 1.0 and 0.7 nm (3σ) and below, respectively. There is not a clear data path performance difference between the investigated PEC methods. After the simulations, the methods were successfully validated in exposures on a MAPPER pre-alpha tool. A 28-nm half pitch Metal-1 and Via-1 layouts show good performance in resist that coincide with the simulation result. Exposures of soft-edge stitched layouts show that beam-to-beam position errors up to AE7 nm specified for FLX 1200 show no noticeable impact on CD. The research leading to these results has been performed in the frame of the industrial collaborative consortium IMAGINE. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/15/2015 Terms of Use: http://spiedl.org/terms

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“…In the MAPPER approach there is the target to realize 13,200 micro-columns within an area of 26mm x 26mm and to have 49 programmable beams within each micro-column which hit the wafer substrate at 5keV beam energy. [14] With each micro-column providing 13nA, the targeted multi-micro-column tool current is ca 170µA. There is the target to cluster 10 micro-column tools to reach 1.7mA beam current.…”

Section: E> E>mentioning

confidence: 99%

Electron multi-beam technology for mask and wafer writing at 0.1nm address grid

Platzgummer

Klein

Loeschner

2013

Alternative Lithographic Technologies V

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An overview of electron beam tool configurations is provided. The adoption of multi-beam writing is mandatory in order to fulfill industrial needs for 11nm HP nodes and below. IMS Nanofabrication realized a 50keV electron multibeam proof-of-concept (POC) tool confirming writing principles with 0.1nm address grid and lithography performance capability. The new architecture will be introduced for mask writing at first, but has also the potential for 1xmask (master template) and direct wafer writing. The POC system achieves the predicted 5nm 1sigma blur across the 82µm x 82µm array of 512 x 512 (262,144) programmable 20nm beams. 24nm HP has been demonstrated and complex patterns have been written in scanning stripe exposure mode. The first production worthy system for the 11nm HP mask node is scheduled for 2014 (Alpha), 2015 (Beta) and 1 st generation HVM mask writer tools in 2016. Implementing a multi-axis column configuration, 50x / 100x productivity enhancements are possible for direct 300mm / 450mm wafer writing.

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Throughput enhancement technique for MAPPER maskless lithography

Cited by 14 publications

References 0 publications

Ice lithography for 3D nanofabrication

Ice lithography for 3D nanofabrication

Demonstration of electronic design automation flow for massively parallel e-beam lithography

Electron multi-beam technology for mask and wafer writing at 0.1nm address grid

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