Throughput analysis of shared-memory crosspoint buffered packet switches

Abstract

This paper presents a theoretical throughput analysis of two buffered-crossbar switches, called shared-memory crosspoint buffered (SMCB) switches, in which crosspoint buffers are shared by two or more inputs. In one of the switches, the sharedcrosspoint buffers are dynamically partitioned and assigned to the sharing inputs, and memory is sped up. In the other switch, inputs are arbitrated to determine which of them accesses the shared-crosspoint buffers, and memory speedup is avoided. SMCB switches have been shown to achieve a throughput comparable to that of a combined input-crosspoint buffered (CICB) switch with dedicated crosspoint buffers to each input but, with less memory than a CICB switch. The two analyzed SMCB switches use random selection as the arbitration scheme. We model the states of the shared crosspoint buffers of the two switches using a Markov-modulated process and prove that the throughput of the proposed switches approaches 100% under independent and identically distributed uniform traffic. In addition, we provide numerical evaluations of the derived formulas to show how the throughput approaches asymptotically to 100%.

Improved analytical model for performance evaluation of crosspoint‐queued switch under uniform traffic

“…Besides, each output port of CQ switches makes arbitrations independently, thus a centralised scheduler with high complexity is not needed, unlike in most input-queued switches [7,8]. Furthermore, CQ switches do not need memory speedup which is required by output-queued and shared-memory switches [9]. When tested under real-trace traffic [10], CQ switches with a feasible crosspoint buffer size can realise a good performance using round robin (RR) or random scheduling algorithms.…”

A computer modeling of the throughput of a crossbar switch by PI-patterns for uniform traffic with variable intensity

“…A part of the current investigations continuing using input buffering with VOQ (Virtual Output Queuing) [5]. Another part of researchers use input and intermediate buffering (CICQ) [6].…”

“…Efficiency check of the algorithms always begins with throughput modeling of the switch node with uniform traffic (uniform i.i.d. Bernoulli) [6,7]. The modeling is necessary to be completed for a large scale of the switch field and in large bandwidth of node loading.…”