Through-Substrate Interconnects for 3-D ICs, RF Systems, and MEMS

Wu, J.H.; Alamo, J.A. del

doi:10.1109/smic.2007.322804

Cited by 17 publications

(10 citation statements)

References 5 publications

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“…Prior works, [13] and [14], examining the capacitance of bulk 3-D vias have neglected two important physical characteristics. The first issue is the formation of a depletion region in the bulk substrate surrounding the TSV, and the second issue is the assumption that the electrical field lines from the 3-D via terminate on a cylinder surrounding the via dielectric liner.…”

Section: Closed-form Capacitance Model Of a 3-d Viamentioning

confidence: 99%

“…Due to the large variation in the 3-D via diameter, length, dielectric thickness, and fill material, a wide range of measured resistances, capacitances, and inductances has been reported in the literature. Single 3-D via resistance values vary from 20 mΩ to as high as 350 Ω [8]- [13], while reported capacitances vary from 2 fF to over 1 pF [14]- [16]. A few researchers have reported measured via inductances that range from as low as 4 pH to as high as 255 pH [9], [13], [16].…”

Section: Introductionmentioning

confidence: 99%

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Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Savidis

Friedman

2009

IEEE Trans. Electron Devices

185

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Abstract-Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.

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Section: Closed-form Capacitance Model Of a 3-d Viamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Savidis

Friedman

2009

IEEE Trans. Electron Devices

185

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“…However, this introduces digital noise into the substrate, which interferes with the operation of RF/analog circuits. This can be mitigated using through-substrate vias wired into a Faraday cage that can suppress crosstalk between blocks [4].…”

Section: Introductionmentioning

confidence: 99%

“…Vias are now completely isolated from the silicon substrate, which was not accomplished using the previous process. This paper represents an augmented version of a preliminary conference presentation of this work [4].…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Characterization of Through-Substrate Interconnects

Alamo

2010

IEEE Trans. Electron Devices

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Abstract-We developed a through-substrate copperdamascene interconnect technology in silicon with minimal impedance. Via impedance was extracted using S parameter measurements at 50 GHz that were matched to simple circuit models. The extracted impedance shows resistances ≤ 1 Ω, recordlow inductance for aspect ratios > 4, and sidewall capacitance that approaches the theoretical value. For an aspect ratio of 10 (10 µm in diameter and 100 µm high), the through-substrate via has an average inductance of 36 pH at 10 GHz, resistance of 0.6 Ω at 1 GHz, and sidewall capacitance of 0.3 pF.Index Terms-Ground inductance, Si RF technology, substrate crosstalk, substrate via, through-substrate via, through-wafer interconnect, through-wafer via, via inductance.

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“…Due to the large variation in the 3-D via diameter, length, dielectric thickness, and fill material, a wide range of measured resistances, capacitances, and inductances have been reported in the literature. Single 3-D via resistance values vary from 20 mΩ to as high as 350 Ω [2]- [6], while reported capacitances vary from 40 fF to over 1 pF [7], [8]. A few researchers have reported measured via inductances that range from as low as 42 pH to as high as 255 pH [3], [9].…”

Section: Introductionmentioning

confidence: 99%

Electrical modeling and characterization of 3-D vias

Savidis

Friedman

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Electrical characterization of the resistance, capacitance, and inductance of inter-plane 3-D vias is presented in this paper. Both capacitive and inductive coupling between multiple 3-D vias is described as a function of the separation distance and plane location. The effects of placing a third shield via between two signal vias is investigated as a means to limit the capacitive coupling. The location of the return path is examined to determine the best placement of a 3-D via to reduce the overall loop inductance. Based on the extracted resistance, capacitance, and inductance, the L/R time constant is shown to be much larger than the RC time constant, demonstrating that the 3-D via structure investigated in this paper is inductively limited rather than capacitively limited.

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Through-Substrate Interconnects for 3-D ICs, RF Systems, and MEMS

Cited by 17 publications

References 5 publications

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Fabrication and Characterization of Through-Substrate Interconnects

Electrical modeling and characterization of 3-D vias

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