Fabrication and Characterization of Through-Substrate Interconnects

Wu, J.H.; Alamo, J.A. del

doi:10.1109/ted.2010.2045671

Cited by 19 publications

(9 citation statements)

References 18 publications

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“…To extract the transmission loss from the test structure, a reference CPW transmission line without any interconnections was fabricated on the front-side of the wafer. The RF measurement results indicate that the CPW integrated with gold-coated nickel wire interconnections offers an excellent RF performance for a very wide band from DC to 66 GHz, which is a much larger operation frequencies as compared to other reported TSVs for RF applications [8,28,29]. The measured maximum return loss at 66 GHz is lower than −10 dB, while the maximum insertion loss is better than −4.62 dB.…”

Section: Aumentioning

confidence: 82%

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Fischer

Bleiker

Somjit

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (> 8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications. IntroductionDuring the past decades, hybrid integration of IC and MEMS technology has been dominated by 2-D approaches, resulting in Multi-Chip Modules (MCM) where different dies are integrated on a single substrate, and System-on-Chip (SoC) solutions where different functionalities are merged onto one die. CMOS and MEMS processing are both well-established and cost-efficient base technologies that are characterized by short development times, low fabrication costs and high yields. Separate manufacturing of CMOS integrated circuit dies and MEMS dies and their subsequent integration into a System-in-Package (SiP) offers high versatility and low process costs, and thus is an attractive alternative to SoC solutions. Especially 3D-integrated System in Package (3D-SiP) solutions, which are based on vertical chip stacking, are a general trend in many integration approaches. Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1,2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3]. 3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors and microphones, CMOS imagers and power LEDs successfully incorporate TSV technology [4][5][6].

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Section: Aumentioning

confidence: 82%

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Fischer

Bleiker

Somjit

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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“…The substrate as well as the insulation material play an important role for the parasitic capacitances. The most commonly used insulator materials are thin layers of silicon oxide or silicon nitride on the via walls [7], [10], [15]- [17]. While these materials provide good elec- trical insulation, their relative permittivities are comparably high, which contributes to high parasitic capacitances.…”

Section: Tsvs For High-frequency Applicationsmentioning

confidence: 99%

“…Already, the first commercially available devices such as MEMS inertial sensors, MEMS microphones, CMOS imagers, and power LEDs successfully incorporate TSV technology [4]- [6]. In the field of millimeter wave applications, however, the development of high-performance TSV interconnections has been lagging behind and has become a bottleneck in circuit performance [7]. Important circuit characteristics such as delay times, impedance matching, and power losses are directly determined by the parasitic impedance of the metal interconnects.…”

Section: Introductionmentioning

confidence: 99%

“…A variety of related research topics are currently under intensive investigation, such as coplanar waveguide (CPW) transition by electromagnetic coupling [8], stacking of waveguide chips by gold bump bonding [9], microstrip transitions by copper TSVs [10], coaxial copper TSVs [11], copper TSV with polymer liner by laser ablation [12], [13], and high current Cu-Cu areaarray interconnections [14]. Conventional TSV concepts use electroplated copper as conductive material and a layer of silicon oxide or silicon nitride as insulator [7], [10], [15]- [17]. However, the manufacturing of copper-plated high-aspect-ratio TSVs has proven to be very challenging [4], [15], [16], [18].…”

Section: Introductionmentioning

confidence: 99%

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High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires

Bleiker

Fischer

Shah

et al. 2015

IEEE Trans. Compon., Packag. Manufact. Technol.

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Abstract-In this paper we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for highfrequency applications. This novel approach is based on magnetic self-assembly of pre-fabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared to conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications such as interposer, MEMS, or millimeter wave applications. For evaluation purposes, coplanar waveguides (CPW) with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from DC to 86 GHz and an insertion loss of less than 0.53 dB per single TSV interconnection for frequencies up to 75 GHz.Index Terms-RF signal transmission, skin effect, vertical interconnection, wafer scale integration, through silicon via (TSV).

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“…As the minimum device dimensions in integrated circuits continue decrease according to Moore's Law and the scaling theory. 1 However, continuing reduce the feature size (as shown in the International Technology Roadmap for Semiconductors (ITRS) requires ILDs with low dielectric constant <2.5 by the <100nm technology node), the increase in crosstalk noise, propagation delay, and power dissipation of the interconnect structure become limiting factors for ultra-large-scale integration (ULSI) of integrated circuits. [2][3][4] The low k materials with attractive mechanical stability, resistance to processing chemicals, low moisture absorption, and high economic efficiency can overcome these problems.…”

Section: Introductionmentioning

confidence: 99%

Electrical characterization of MIM capacitor comprises an adamantane film at room temperature

Tiwari

Yoshimura

2016

AIP Advances

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We fabricated a new metal-insulator-metal capacitor at room temperature, comprising a ∼90 nm thin low–k adamantane film on a Si substrate. The surface morphology of deposited organic film was investigated by using scanning electron microscopy and Raman spectroscopy, which is confirmed that the adamantane thin film was uniformly distributed on the Si surface. The adamantane film exhibits a low leakage current density of 7.4 x 10−7 A/cm2 at 13.5 V, better capacitance density of 2.14 fF/μm2 at 100 KHz.

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Fabrication and Characterization of Through-Substrate Interconnects

Cited by 19 publications

References 18 publications

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires

Electrical characterization of MIM capacitor comprises an adamantane film at room temperature

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