Through silicon vias technology for CMOS image sensors packaging

Henry, David D.; Jacquet, F.; Neyret, M.; Baillin, Xavier; Enot, T.; Lapras, V.; Brunet-Manquat, C.; Charbonnier, Jean; Aventurier, Bernard; Sillon, N.

doi:10.1109/ectc.2008.4550028

Cited by 68 publications

(25 citation statements)

References 3 publications

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“…More details can be found in previous publications [7,8]. The post-process for via-last technology included the following main technological steps:…”

Section: General Process Descriptionmentioning

confidence: 99%

Integration of a temporary carrier in a TSV process flow

Charbonnier

Chéramy

Henry

et al. 2009

2009 59th Electronic Components and Technology Conference

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wafer stacking technologies offer new possibilities in terms of device architecture and miniaturization [1][2][3]. To stack wafers, reliable throughsilicon vias (TSVs) and interconnections must be processed into ultrathin wafers, and such processing is made possible by new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives can offer a variety of properties sufficient for withstanding the TSV processes: flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning processes. This paper demonstrates that, contrary to tapes and waxes currently used for temporary bonding, a new removable high-temperature adhesive  meets all the requirements named above for reliable TSV processing on 8-inch active wafers. We will first describe formation of TSVs with aspect ratios of 1:1 and 2:1 into thinned wafers. IntroductionTo be successful, 3-D ultrathin wafer stacking technologies require the development of reliable through-die interconnects with varying aspect ratios depending on the application. This type of integration poses forward new challenges in the development of new TSV processes suitable for thin-wafer handling technologies.It has already been demonstrated in a previous publication [4] that a temporary bonding process using new hightemperature adhesives  could provide an innovative and robust solution to produce functional 1:1 aspect ratio TSVs in 70-micron-thick silicon wafers. This first result showed that in addition to presenting sufficient thermal and mechanical properties to withstand all the backside process steps, the high-temperature adhesive enables easy bonding, debonding, and cleaning processes.Although encouraging, these first results obtained on plain silicon wafers were not completely representative of TSV integration in industrial products. Indeed, due to the presence of several metallization and passivation layers, an active CMOS-containing wafer can present a different deformation behavior compared to a plain wafer when heated, which can weaken its adhesion to the temporary layer during the process. Therefore the purpose of this paper is to assess the TSV creation on temporarily bonded complex active wafers.In the first part of this paper, we will assess the full TSV realization on device wafers thinned to 70 microns thanks to a temporary bonding process. The active wafers used were

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“…More details can be found in previous publications [7,8]. The post-process for via-last technology included the following main technological steps:…”

Section: General Process Descriptionmentioning

confidence: 99%

Integration of a temporary carrier in a TSV process flow

Charbonnier

Chéramy

Henry

et al. 2009

2009 59th Electronic Components and Technology Conference

Self Cite

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“…A monolayer CIS chip with TSVs has been already in volume production [34]. Backvia type TSVs with large diameter are used in this CIS chip.…”

Section: D-stacked Cmos Image Sensormentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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“…Three dimensional (3D) integration circuit technology affords significant promise to release the power, improve the performance and computational tradeoffs inherent in conventional planar circuit topologies, and makes through silicon via (TSV) appear to be one of the greatest technology challenges, inspiringly, the TSV technology has been successfully applied in CMOS image sensors (CIS) widely [1,2]. However, the aspect ratio of TSV for CIS is much smaller than that for interposer.…”

Section: Introductionmentioning

confidence: 98%

Fabricating polymer insulation layer by spin-coating for through silicon vias

Zhang

Jiang

Liu

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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This paper reports a fabrication process for the deposition of a polymer insulation layer on the sidewall of through silicon vias in wafer level packaging. The novolac resin based glue was used as precursor to prepare the insulation layer. The glue is a Newtonian fluid and has low viscosity (24 mPa*s @ 100 l/s) as well as low contact angle (25.9 o ) to silicon. The resultant polymer insulation layer has a shearing strength as high as 25.8 Kg/mm 2 . Furthermore, the polymer insulation layer exhibits good uniformity in thickness and roughness over the whole 8'' wafer. On the conformal coating of the polymer insulation layer, the Ti/Cu seed layer and Cu conductive layer were fabricated by PVD and electroplating. Therefore, all the results show that the polymer materials could be a reliable and economical solution for the TSV insulator in the view of wafer level packaging. IntroductionThree dimensional (3D) integration circuit technology affords significant promise to release the power, improve the performance and computational tradeoffs inherent in conventional planar circuit topologies, and makes through silicon via (TSV) appear to be one of the greatest technology challenges, inspiringly, the TSV technology has been successfully applied in CMOS image sensors (CIS) widely [1,2]. However, the aspect ratio of TSV for CIS is much smaller than that for interposer. Therefore, there are several options for fabricating conformal insulation layer on wafer level packaging.

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Through silicon vias technology for CMOS image sensors packaging

Cited by 68 publications

References 3 publications

Integration of a temporary carrier in a TSV process flow

Integration of a temporary carrier in a TSV process flow

Recent progress in 3D integration technology

Fabricating polymer insulation layer by spin-coating for through silicon vias

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