Through Silicon Via Reliability

Effects of Bosch scallops on metal layer stress of an open Through Silicon Via technology

“…Metallization and SiO 2 passivation are deposited conformally on the TSV surfaces following the Si etch process. More processing details can be found in the work of J. Kraft et al [8]. The metal layers were composed of tungsten (W) and Ti/TiN thin films with thickness of 100 nm and 95 nm, respectively (Fig.…”

“…A device has usually several vias close to each other, which can be arranged in a such way so that stress is mutually cancelled or reduced among them. It was recently introduced a 3D integration technology based on open TSV [5], and since then several papers have been published about its mechanical [5][6][7] and electrical properties [8]. So far, the structure has proved itself to be reliable and mechanical stable, but a recent paper of Krauss [6] reported an uncommon behavior of the stress in the via.…”

Optimization of through silicon via for three-dimensional integration

“…Though copper electroplating technology for TSV filling has been studied extensively, it is still a challenge to provide void-free filling in TSVs with a high aspect ratio, where incorporated seams or voids in the vias will ultimately cause serious reliability issues [14][15][16]. Discontinuous seed layer deposition, insufficient wettability of the TSV before plating and uneven distribution of local current density are the major reasons for defects http formation [17][18][19].…”

Electromigration-induced failure in operando characterization of 3D interconnects: microstructure influence

“…Few experimental works have been focused on electromigration in structures with this technology [11][12][13]. They all state the absence of voids inside the TSV.…”