Effects of Bosch scallops on metal layer stress of an open Through Silicon Via technology

Abstract

Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. The presence of scallops on the TSV wall modifies the stress distribution along the via. By means of Finite Element Method (FEM) simulations, we could assess this change and understand the process. The achieved results support experiments and give a better insight into the influence of scallops on the stress in an open TSV.

Nanostructural Analysis of CMOS-MEMS-Based Digital Microphone for Performance Optimization

“…Also, wet chemical cleaning step should be included in process flow to remove etch by-products; (2) Addition of Cu in Al or replacing Al by Cu interconnect technology with good barrier/adhesion layers (e.g., thin amorphous Si:C:H films) would have benefits of lower electromigration (higher life-time), fewer hillocks (less short between interfaces) and lower resistivity (reduced RC delay) [29]; (3) to mitigate stress-induced delamination (hillocks), selection of non-metallic barriers (e.g., SiCN or TaN) would have advantage over metal barriers because of their closely matched CTE to dielectric substrates. Also, in W-TSV technology, Bosch scallops might be helpful for stress reduction in metal layers [30]; (4) embed low-k dielectrics (air or porous silica xerogel), for instance, air-gaps during ILD deposition, would help in better electromigration reliability (stress relaxation by free space) and lower interconnect capacitance [31]; (5) to minimize the grain boundary diffusion, bamboo-shaped grain structure need to developed during thin-film production or SiN combination with SiO 2 to minimize that issue; (6) SEM-based TKD-EDS should be included as part of failure analysis tools because these sophisticated microanalytical techniques can identify the correlations with the chemistry and crystallography of prospective nanomembrane MEMS or ultra-large-scale integration (ULSI) circuits.…”

Stress estimation in open tungsten TSV

“…High stress in this layer can lead to failure of the entire via, especially in the presence of Bosch scallops [6], [7]. During metal deposition, stress arises as result of physical mechanisms which take place during film growth.…”

“…We have investigated mechanical aspects of this structure in several previous papers [5], [6], [7]. Other works have explored the electrical properties [2], processing [4], and experimental mechanical characterization [8] of this technology.…”