Through-Silicon-Via Fabrication Technologies, Passives Extraction, and Electrical Modeling for 3-D Integration/Packaging

Xu, Zheng; Lü, Jian–Qiang

doi:10.1109/tsm.2012.2236369

Cited by 68 publications

(26 citation statements)

References 25 publications

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“…The S-parameters are now used to extrapolate key transmission line parameters such as attenuation and phase constant. By employing the methods described by Xu [16], the S/G TSV S-parameters are converted to RLGC parameters. With the RLGC parameters known, the transmission line propagation constant is computed in accordance with Equation (1).…”

Section: Resultsmentioning

confidence: 99%

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

Adamshick¹,

Carroll²,

Rao³

et al. 2014

PIER Letters

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Abstract-3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging efficiency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Specifically, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior. In this letter, 5 × 50 µm TSVs are manufactured using a via-mid integration scheme and characterized using S-parameters up to 65 GHz. At 50 GHz, the measured attenuation constant is 0.35 dB/via with a time delay of 0.7 ps/via.

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Section: Resultsmentioning

confidence: 99%

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

Adamshick¹,

Carroll²,

Rao³

et al. 2014

PIER Letters

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“…3D integration often relies on Through-Silicon Via (TSV) technology. However, TSVs can occupy significantly large area footprint [Xu13] (e.g., 6.25 compared to area of a 2-input NAND gate standard cell for 28nm technology). Moreover, they require large keep-out-zones where no transistors may be placed.…”

Section: D Integrationmentioning

confidence: 99%

Nano-engineered architectures for ultra-low power wireless body sensor nodes

Braojos

Atienza

Aly

et al. 2016

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Wireless body sensor nodes (WBSNs) are miniaturized devices that are able to acquire, process and transmit bio-signals (such as electrocardiograms, respiration or human-body kinetics). WBSNs face major design challenges due to extremely limited power budgets and very small form factors. We demonstrate, for the first time in the literature, the use of disruptive nanotechnologies to create new nano-engineered ultra-low power (ULP) WBSN architectures. Compared to state-of-the-art multi-core WBSN designs, our new architectures dramatically reduce power consumption by 5.42x and footprint by 5x, while fulfilling realtime processing requirements of bio-signal monitoring applications. Our WBSN architectures achieve these results by utilizing emerging non-volatile memory technologies (such as resistive RAM and spin-transfer torque RAM) and their ultradense and fine-grained three-dimensional integration with logic (such as monolithic three-dimensional integration naturally enabled by carbon nanotube field-effect transistors).

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“…While there have been many studies on this topic [11][12][13][14], our analysis includes more details in order to fine-tune our TSV process development and optimization. For example, we included in our model the often-ignored barrier layer in the TSV metallization.…”

Section: Electrical Simulationmentioning

confidence: 99%

TSV module optimization for high performance silicon interposer

Cao¹,

Dinan²,

Sun³

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper presents Invensas' silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low temperature oxide (LTO) and low temperature polyimide (LTPI) passivation. IntroductionEach generation of semiconductor products from cellphones to servers is expected to be faster and more powerful than the previous one. Along with the everexpanding internet and widespread availability of portable devices, more computing power and functionality need to be available in small packages. The number of diverse chips inside these products is increasing rapidly and their integration within a small form factor is driving dense chip packaging technology, such as multi-chip modules (MCM), package on package (POP), package in package (PIP) and 3D integration.2.5D integration using a silicon interposer offers a way to achieve dense chip packaging with high performance interconnects for these applications. The benefits include smaller foot print, lower power consumption, and shorter delays. Silicon interposer can also reduce stress and warpage caused by CTE mismatch between chips and package substrate. Chips built with different process flows, such as logic memory, CMOS image sensor (CIS) and microelectro mechanical systems (MEMS) can be closely connected using the top routing layer of an interposer. Since chips are placed side by side on an interposer, this assembly method reduces the thermal issues of high-power 3D stacked dies.The market for 2.5D technology includes FPGA, ASIC, CPU, GPU, APU, high end memory and mobile applications. A number of companies are working on TSV interposer technology [1][2][3][4][5][6][7][8][9], and close to 80 million interposer based products are expected to be fabricated in 2014 [10]. Invensas is also developing technology for this growing market. There are many technical challenges in TSV interposer manufacturing. This paper describes our interposer test vehicle and our process optimization results.

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Through-Silicon-Via Fabrication Technologies, Passives Extraction, and Electrical Modeling for 3-D Integration/Packaging

Cited by 68 publications

References 25 publications

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

High Frequency Electrical Characterization of 3d Signal/Ground Through Silicon Vias

Nano-engineered architectures for ultra-low power wireless body sensor nodes

TSV module optimization for high performance silicon interposer

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