Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs

Abstract

Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied thoroughly in the literature. In this paper, we analyze the impact of TSVs on silicon area and wirelength. We derive a new 3D wirelength distribution model considering TSV size. Based on this new prediction model, we explain the impact of several design parameters newly introduced in 3D ICs. We also present a case study to show how the model can help make early design decisions for 3D ICs.

Assembling 2-D Blocks Into 3-D Chips

“…Its adverse effects include the massive number of necessary TSVs for random logic, as discussed in Section 2. The study by Kim et al [16] reveals that partitioning gates between multiple dies may undermine wirelength reduction unless circuit modules of certain minimal size are preserved. In addition, partitioning a design block across multiple dies means it cannot be fully tested before die stacking.…”

“…Furthermore, manufacturability demands landing pads and keep-out zones [31] which further increase TSV area footprint. At the 45nm technology node, the area footprint of a 10µm × 10µm TSV is comparable to that of about 50 gates [16]. Hence, 10,000 TSVs can displace half a million gates.…”

“…While the usage of TSVs is generally expected to reduce total wirelength, Kim et al [16] observe that wirelength reduction varies depending on the number of TSVs and their characteristics. They show that TSV insertion in general and the impact of TSV footprint area in particular may increase silicon area and/or routing congestion, thereby making wires longer.…”

“…Consequently, Kim et al propose a new wirelength distribution model to estimate wirelength reduction while considering the impact of TSVs on wirelength. Case studies in [16] show that excessive usage of TSVs can undermine their potential advantages, and that this trade-off is controlled by the granularity of inter-die partitioning. The wirelength typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but increases for fine (gate-level partitioning) granularities.…”

“…Via-first TSVs occupy the device layer, resulting in placement obstacles, while via-last TSVs occupy both the device and metal layers, resulting in placement and routing obstacles [16]. Hence, TSVs must be accounted for during floorplanning and/or placement.…”