Threshold voltage control in NiSi-gated MOSFETs through SIIS

Abstract

Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.

Dependence of Effective Work Function Modulation with Phosphorous Segregation on Ni to Si Ratio in Ni Silicide/SiO2 Systems

“…In the conventional P incorporation process, P ions are implanted into a poly-Si gate before Ni silicide gate formation and introduced to the Ni silicide/SiO 2 interface with the ''snow-plow effect'' during silicidation (pre-doping process). [1][2][3][4][5][6][7]12) However, not only P segregation but also changes in crystallinity and Ni-Si ratio of the silicide layer occur in the pre-doping process. 6,8) These changes of the film structure make it difficult to evaluate the unadulterated effect of P segregation, since they are also possible causes of È eff modulation.…”

“…The observation that the slopes of V fb vs EOT relations are almost the same indicates little changes in fixed charge densities at the SiO 2 /Si(100) interface. In the Ni 2 Si (Ni 3 Si 2 )/SiO 2 and NiSi/SiO 2 systems, the V fb values shift to the negative direction and the evaluated È eff s from the y-intercept decrease with P segregation similarly to those of P pre-doped cases; 1,[4][5][6][7] the È eff changes from 4:70 AE 0:01 to 4:38 AE 0:01 eV at Ni 2 Si (Ni 3 Si 2 )/SiO 2 interface, and from 4:66 AE 0:01 to 4:37 AE 0:01 eV at the NiSi/SiO 2 interface. We found that È eff also decreases with P segregation in the NiSi 2 /SiO 2 system, and the largest ÁÈ eff of À0:45 eV was obtained with the realization of the lowest È eff value of 4:13 AE 0:04 eV, which is close to Si-E c suitable for nMOS devices.…”

“…A nickel fully silicided (Ni-FUSI) gate is a good candidate for the metal gate electrode because of its process compatibility with the present large-scale integration fabrication and superior device performance. [1][2][3][4] The difficulty of effective work function (È eff ) control at the Ni-FUSI/gate dielectric interface is one of the major impediments to the application of a Ni-FUSI gate for future CMOS devices. È eff s corresponding to the Si conduction band edge (Si-E c $ 4:1 eV) and Si valence band edge (Si-E v $ 5:2 eV) are required for n-and p-type transistors to realize low threshold-voltage (V th ) operation in bulk CMOS devices, whereas the È eff of NiSi is about 4.6 eV, which corresponds to Si midgap level.…”

“…The È eff of the Ni-FUSI gate can be controlled by impurity segregation at Ni-FUSI/SiO 2 and SiON interfaces. [1][2][3][4][5][6][7][8] È eff decreases with increasing interface densities of arsenic (As), phosphorus (P), and antimony (Sb). On the other hand, È eff increases with increasing B interface density.…”

Influence of Ni silicide phases on effective work function modulation with Al-pileup in the Ni fully silicided gate/HfSiON system

“…[2][3][4] Ni-FUSI gate structure can be realized by modification of today's selfaligned silicidation technology without novel metaldeposition and gate-etching processes, resulting in reduced CMOS fabrication process complexity.…”