Threshold voltage and subthreshold slope of the volume-inversion MOS transistor

Brini, J.; Benachir, M.; Ghibaudo, G.

doi:10.1049/ip-g-2.1991.0025

Cited by 10 publications

(2 citation statements)

References 5 publications

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“…However, these experimental results have been obtained with different biases applied to the front and back gates due to the different front-and back-gate oxides, and we have shown that an application of V g2 /V g1 proportional to t ox2 /t ox1 gives an overestimation of the performance of the devices [41]. Single-gate, double-gate, and GAA InAs TFETs lead to very good simulated results (for…”

Section: Tunnel Fetsmentioning

confidence: 87%

“…The facts that the current drive of the VI-MOSFET is governed by two, three, or four gates and that carriers are no longer confined at one interface present remarkable advantages: enhancement of the number of minority carriers, increase in carrier mobility and velocity due to reduced influence of scattering associated with oxide charges and surface roughness, increase in drain current and transconductance, reduced short-channel effects, and ideal subthreshold slope [22,23]. The subthreshold slope S vi and threshold voltage V t of the VI-MOSFET are calculated using a constant potential in the whole silicon layer [13,24], which is a very good approximation for V g V t :…”

Section: Ultimate Device Architecturesmentioning

confidence: 99%

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Ultralow-Power Device Operation

Balestra

2015

Nanoscale Materials and Devices for Electronics, Photonics and Solar Energy

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The historic trend in micro/nano-electronics these last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition. We are facing today dramatic challenges dealing with the limits of energy consumption and heat removal, inducing fundamental tradeoffs for the future ICs. A substantial reduction of the static and dynamic power is strongly needed for the development of future high-performance/ultralow-power terascale integration and autonomous nanosystems.This chapter of the tutorial book addresses the main trends, challenges, limits, and possible solutions for strongly reducing the energy per binary switching. Several paths are possible, the most promising one being the reduction of static and dynamic energy consumption using conventional logic with a reduction in the stored energy and therefore a decrease of device capacitance C (device integration) and applied bias V, together with a decrease of leakage currents of nanodevices.The best potential solutions are ultrathin-film SOI (silicon-on-insulator) and multi-gate devices, nanowires, and small-slope switches (tunnel FETs, ferroelectric gate FETs, NEMS) using alternative channel, source/drain, and gate materials. We will present the main challenges to continue More's law, the novel materials and device architectures, and the possible combination of these boosters, needed for the development of future ultralow-power ICs.

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Section: Tunnel Fetsmentioning

confidence: 87%