Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Kim, Yoon; Yun, Jang−Gn; Park, Se Hwan; Kim, Wandong; Seo, Joo Yun; Kang, Myounggon; Ryoo, Kyung−Chang; Oh, Jeong-Hoon; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung‐Gook

doi:10.1109/ted.2011.2170841

Cited by 65 publications

(23 citation statements)

References 12 publications

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“…Thus, through the CTF memory device as well as FG one cannot scale down in a linear manner. Memory integration density may, however, further increase by a 3-D approach of stacking memory array that can be confirmed in recent papers [1]- [4]. Previously, we verified the suitability as a technology enabling continuous scaling and performance superiority of 3-D single-crystalline channel stacked array (CSTAR) by stringent 3-D technology computeraided design works and comparison studies.…”

Section: Introductionsupporting

confidence: 67%

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Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

Kim

Kang

Park

et al. 2013

IEEE Electron Device Lett.

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This letter describes 3-D NAND flash memory architecture having four-level stacked single-crystalline silicon nanowire channels. Previously, we designed 3-D NAND flash memory architecture based on single-crystalline channel stacked array (CSTAR). In this letter, CSTAR NAND flash memory is fabricated and its operations are verified. Successful memory operations of each stacked array of CSTAR including program/erase, retention, and endurance performances are demonstrated. Index Terms-3-D NAND flash memory, memory operation, nanowire SONOS, stacked array.

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Section: Introductionsupporting

confidence: 67%

“…1(b) shows the fabrication flow. The specific method in each step is evolved and refined from a previous research [1]. In the process integration for fabricating CSTAR flash memory, silicon germanium (SiGe) selective etching is one of the most critical steps.…”

Section: Introductionmentioning

confidence: 99%

Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

Kim

Kang

Park

et al. 2013

IEEE Electron Device Lett.

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“…The structure of 3D NAND flash memory is based on an ultra-thin body (UTB) structure in which the channel of the main cell is not connected to the body, and body bias is not applicable to the channel of the main cell. This can cause the channel to float, resulting in the down coupling phenomenon (DCP) and natural local self-boosting (NLSB) phenomena [5][6][7][8]. When program voltage (V PGM ) is applied to selected word-line (WL) of 3D NAND flash memory, program operation should not be performed on the selected WL of inhibit string.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

et al. 2020

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Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical potential boosting. In addition, in the region of the middle cells (WL6 through WL10), a slight change in the potential boosting was also almost the same. In the 3D NAND, where there was a dummy WL (DWL), the NLSB for the edge WL changed as the pattern of the DWL changed. The DWL did not affect the NLSB of the main cell, regardless of the pattern. Therefore, the high potential of the edge WL could reduce the potential difference between the main cell and the edge WL using the DWL.

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“…1 Previous studies were reported that 3D integration has already been widely used in CMOS image sensor, NAND flash, etc. [2][3][4][5] 3D integration can be realized by vertical interconnections between the stacked layers using metal bonding techniques. 6 As chip size becomes smaller and I/O density gets higher, there is an urgent desire to develop metal bonding technique suitable for ultra-fine pitch interconnection.…”

Section: Introductionmentioning

confidence: 99%

Low temperature Cu-Cu bonding using copper nanoparticles fabricated by high pressure PVD

Cai

Wang

et al. 2017

AIP Advances

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Copper nanoparticles (Cu NPs) fabricated by physical vapor deposition (PVD) were introduced in Cu-Cu bonding as surface modification. The bonding structure with Ti adhesive/barrier layer and Cu substrate layer was fabricated on both surfaces first. Loose structure with Cu NPs was then deposited by magnetron sputtering in a high pressure environment. Solid state Cu-Cu bonding process was accomplished at 200°C for 3min under the pressure of 20MPa. Die shear test was carried out and an average bonding strength of 36.75MPa was achieved. The analysis of fracture surface revealed a high-reliability bonding structure. According to cross-sectional observations, a void-free intermediate Cu layer with thickness around 10nm was obtained. These results demonstrated that a reliable low temperature time-saving Cu-Cu bonding was realized by Cu NPs between the bonding pairs. This novel bonding method might be one of the most attractive techniques in the application of ultra-fine pitch 3D integration.

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Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Cited by 65 publications

References 12 publications

Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

Low temperature Cu-Cu bonding using copper nanoparticles fabricated by high pressure PVD

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