Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

Abstract

This letter describes 3-D NAND flash memory architecture having four-level stacked single-crystalline silicon nanowire channels. Previously, we designed 3-D NAND flash memory architecture based on single-crystalline channel stacked array (CSTAR). In this letter, CSTAR NAND flash memory is fabricated and its operations are verified. Successful memory operations of each stacked array of CSTAR including program/erase, retention, and endurance performances are demonstrated. Index Terms-3-D NAND flash memory, memory operation, nanowire SONOS, stacked array.

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

“…BLs of selected strings are biased at 0 V [2]. On the other hand, each stacked channel in our proposed Channel STacked ARray (CSTAR) structure [26] is connected with different BL as depicted in Fig. 5.7.…”

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

“…On the other hand, each stacked channel in our proposed Channel STacked ARray (CSTAR) structure [4] is connected with different BL as depicted in Fig. 9(a).…”

“…To overcome NAND scaling issues, three-dimensional (3D) stacked NAND array has been considered as a breakthrough. A number of 3D stacked NAND array architectures have been reported [1][2][3][4], and chnnel stacked array architecture is one of the representative architectures, which features single crystalline silicon channel and Gate-All-Around (GAA) structure. Although its high on-current level and device scalability is demonstrated, there is an issue on cell size variation between layers induced by the etch slope.…”

“…Fig. 1 shows the cross-sectional FESEM (Field Emission Scanning Electron Microscope) images of the fabricated STacked ARray (STAR) devices having Sinanowire channel and GAA structure [4]. Due to the declined etch slope, the cross sections of the stacked channels are not circular but elliptical with different geometry eccentricity.…”

Novel hybrid 3D NAND flash memory containing vertical-gate and gate-all-around structures

“…It exhibits high feasibility of increasing the bit density and saving bit cost. Nowadays, several 3D memory structures including bit-cost scalable (BiCS) NAND [1][2][3], pipe-shaped bit-cost scalable (p-BiCS) NAND [4][5][6], terabit cell array transistor (TCAT) [7], STacked ARray (STAR) [8][9][10], and VG-NAND [11][12][13] have been proposed, demonstrated or even mass produced. Among them, VC and VG devices are fabricated by creating vertical and horizontal Si channels as bitlines.…”