Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis

Abstract

Abstract-Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools, the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the floorplan and the P/G network concurrently. Most current 3D IC floorplanners neglect the effects of the 3D P/G network on the design, which may lead to large IR drops in the circuit. To create feasible floorplans with efficient P/G networks, the 3D Floorplan and P/G Co-synthesis tool optimizes the floorplan in terms of wirelength, area and P/G routing area and IR drops. The tool integrates a 3D B*-tree floorplan representation, a resistive P/G mesh, and a Simulated Annealing (SA) engine to explore the 3D floorplan and P/G network. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool show that 3D ICs tend to increase the P/G routing area while decreasing the IR drops in the circuit. By considering the IR drop while floorplanning, exploring the 3D P/G design space, and evaluating 3D IC's effect on 3D P/G networks, the 3D Floorplan and P/G Co-synthesis tool can develop a more efficient 3D IC.

Advancing the thermal stability of 3D ICs using logi-thermal simulation

“…3D ICs have the advantage of making large scale integration possible at a small footprint which reduces prices both by simplifying testing and making PCBs decrease in size. The average wire length is also reduced, although the interconnections between layers have a considerably larger capacitance than indie wires [2]. By keeping signals within the package the power consumption is also cut down while the operating frequency is higher.…”

Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm

“…A lot of work has been done in 2D and 3D floorplan optimization, as in [5], [7], [8], [9], [10], [11], [12], [13], and [14]. However, in all those works, temperature and IR-Drop are the design goals.…”

Machine Learning Based Variation Modeling and Optimization for 3D ICs

“…However, as with every new technology, 3D ICs come with new issues like high power density leading to thermal and power delivery issues [3,4], modeling of 3D parasitics which is under research and not yet fully developed, and lack of CAD tools for actual 3D place and route. Another major difference when compared to 2D ICs is the addition of die-todie variations in TSV-based 3D ICs where the different dies are stacked together and data/clock paths run across multiple dies (Fig.…”