Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Siozios, Kostas; Soudris, Dimitrios; Economakos, George

doi:10.1109/icdsp.2009.5201124

Cited by 3 publications

(3 citation statements)

References 13 publications

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“…More info regarding the features of proposed methodology of application mapping under different design constraints (timing-aware, power-aware, etc) onto 3D FPGAs can be found in [9], [10], [11], [12].…”

Section: D Fpga Flowmentioning

confidence: 99%

CAD tools for designing 3D integrated systems

Siozios

Papanikolaou

Soudris

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Expectations of consumer for future consumer electronics devices put significant strain on conventional design and manufacturing processes. Integrating more functionality in a smaller form factor with lower power consumption and cost is pushing traditional semiconductor technology scaling to its limits. Three dimensional chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. This paper outlines a generic methodology to design 3D systems.

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Section: D Fpga Flowmentioning

confidence: 99%

CAD tools for designing 3D integrated systems

Siozios

Papanikolaou

Soudris

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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“…This architecture is called CNPGA in this paper. Considerable researches have been reported on separating the routing resources in many modern FPGA technologies, especially in three-dimensional chips [20]. CNFET-based routing switches in the proposed architecture may be fabricated on a CMOS wafer or can be constructed as an auxiliary layer in a threedimensional chip.…”

Section: The Proposed Hybrid Fpga Architecturementioning

confidence: 99%

Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale

2011

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Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors (CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes. Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31% smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

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“…In the context of GPPs, interface between the L2 cache and main memory is architected using 3D interconnect technology, and performance is compared to a 2D design for memoryintensive applications [6][7][8][9][10]. In the context of FPGAs, a number of recent studies have shown that 3D FPGAs have better performance than existing 2D designs [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Domain-specific processor with 3D integration for medical image processing

Cong

Guruaj

Huang

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-The growth of 3D technology had led to opportunities for stacked multiprocessor-accelerator computing platforms with highbandwidth and low-latency TSV connections between them, resulting in high computing performance and better energy efficiency. This work evaluates the performance and energy benefits of such an advanced architecture and addresses associated design problems. To better utilize the reconfigurable hardware resource and to explore the opportunity of kernel sharing across applications, we propose to use a dedicated domain-specific computing platform. In particular, we have chosen medical image processing as the domain in this work to accelerate due to its growing for real-time processing demand yet inadequete performance on conventional computing architectures. A design flow is proposed in this work for the 3D multiprocessoraccelerator platform and a number of methods are applied to optimize the average performance of all the applications in the targeted domain under area and bandwidth constraints. Experiments show that the applications in this domain can gain a 7.4x speed-up and 18.8x energy savings on average running on our platform using CMP cores and domain-specific accelerators as compared to their counterparts coded in CPU only.

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Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Cited by 3 publications

References 13 publications

CAD tools for designing 3D integrated systems

CAD tools for designing 3D integrated systems

Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale

Domain-specific processor with 3D integration for medical image processing

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