Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale

Abstract

Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors (CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes. Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31% smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells

“…12 Similar to MOSFETs, CNFETs have also two kinds of transistors, p-type and n-type; they have equal motility with the same transistor geometry that it makes easy transistor sizing of complex digital circuits. 13 Moreover, the current-voltage (I -V ) characteristic of a CNFET device is similar to I -V characteristics of MOSFET device. Finally, there is a remarkable advantage that makes CNFET to have more advantages against other technologies.…”

Flattening: An efficient approach to improving the performance of conventional MINs

“…The simulations of the networks were processed at the gate level (not at the transistor level). Therefore, the only way of performance evaluation for these networks using CNT technology was comparison with the results of the previous studies [35][36][37]. Fig.…”

“…16 illustrates the delay of the critical path in different networks in CNT and CMOS technologies. We used the results of a previous study [35] to estimate the delay of the critical path of the networks. The technology size for both of CMOS and CNT is equal to 22 nm.…”

“…The flattened Omega network has the lowest power consumption because of the small size of its routers. Similar to the calculation of the critical path delay, the power consumption of networks was calculated using the results of a previous research work [35]. CNT technology decreases the networks power consumption by 8%.…”

Analytical performance evaluation of molecular logic circuits

“…Applications such as full adder cell [10][11][12], multiple-valued logic circuits [13], low power SRAM cell [14], FPGA switches [15], current mode circuits [16] and combinational circuits [17] have been presented via carbon nanotube transistors (CNFET).…”