Thin Film Deposition for Front End of Line

Belyansky, M.

doi:10.1016/b978-0-12-812311-9.00008-6

Cited by 10 publications

(4 citation statements)

References 73 publications

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“…X-ray diffraction spectroscopy is the characterization technique used to determine the atomic and molecular structure of crystal materials. 29 The XRD spectrum of GO showed an intense diffraction peak at 2 θ = 11.2° with an interlayer distance of 7.9 Å along with the appearance of small non-oxidized graphene peak at 2 θ = 26.1° with d spacing of 3.5 Å (Fig. 3a).…”

Section: Resultsmentioning

confidence: 99%

Fluorene intercalated graphene oxide based CoQ10 imprinted polymer composite as a selective platform for electrochemical sensing of CoQ10

et al. 2022

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Section: Resultsmentioning

confidence: 99%

Fluorene intercalated graphene oxide based CoQ10 imprinted polymer composite as a selective platform for electrochemical sensing of CoQ10

et al. 2022

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“…In the context of high-product-mix manufacturing, the chemical vapor deposition processes face formidable challenges characterized by variations in deposition thickness attributed to both the design layout of devices and the conditions within chemical vapor deposition (CVD) process chambers. As emphasized in Figure 2(a), the irregularities in film thickness between single and double pitches are distinctly evident [1]. Furthermore, Figure 2(b) presents transmission electron microscopy (TEM) images that effectively demonstrate variations in silicon nitride film thickness between patterns of wide and narrow widths [2].…”

Section: Chemical Vapor Deposition (Cvd) Process Challengesmentioning

confidence: 92%

“…The lack of precise control over thickness across diverse array of layout designs, in conjunction with resultant film variability, holds the potential to significantly influence critical transistor parameters such as threshold voltage and overlap capacitance. This, in turn, can ultimately lead to the undesirable consequence of yield loss [1].…”

Section: Chemical Vapor Deposition (Cvd) Process Challengesmentioning

confidence: 99%

Advanced process control by machine learning-based virtual metrology for high product mix manufacturing

Lee,

Choi,

Greeneltch

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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The semiconductor foundry industry struggles with challenges in high-product-mix manufacturing, necessitating enhanced flexibility to address diverse customer demands. Coordinating multiple chambers and process steps with varying designs and technology nodes poses complexities leading to reduced yields and increased costs. The chemical vapor deposition (CVD) process introduces thickness variations due to device layout design and chamber condition drift, impacting transistor parameters and yield. Managing chamber-by-chamber variations is critical for high-volume manufacturing, yet traditional solutions fall short in fab line management, resulting in throughput loss. Conventional VM relies on data from the process chamber, referred to as fault detection and classification (FDC), to predict metrology results. In this study, the extraction of design features for better predictive purposes across diverse layouts and technologies are highlighted. Siemens' Calibre® software is employed for design feature extraction, and machine learning (ML) methodologies to construct the extended VM model. An advanced process control (APC) system using the extended VM model for run-to-run (R2R) control is proposed. It incorporates design features, FDC, and measurements to achieve the desired thickness target. The system triggers updates to the extended VM model based on prediction errors. Through control simulations, the APC system significantly enhances process capability and reduces film thickness variations, confirming its effectiveness in a high-mix product foundry fab. Responding to the growing demand for custom-designed products, this paper suggests integrating an ML-based extended VM model with design features and FDC into the APC system, presenting a promise solution for high-product-mix manufacturing.

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“…These contacts are traditionally formed by in-situ doped polysilicon deposition and recess in the contact holes or trenches before metallization. With the continuous downscaling of DRAM array transistor dimensions, the polysilicon deposition filling in those small contact regions may show some voids or seams (38) which may impact contact resistivity and therefore the overall performance of DRAM operation. Figure 15 shows a schematic DRAM array structure highlighting the SNC region contacting the DRAM array to the capacitors.…”

Section: Memorymentioning

confidence: 99%

(Invited) Laser Thermal Annealing for Low Thermal Budget Applications: From Contact Formation to Material Modification

et al. 2019

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Pulsed laser thermal annealing at the nanosecond timescale was successfully introduced into semiconductor devices manufacturing in the late 2000s for high volume manufacturing of sensitive 3D architectures such as vertical Si-based Insulated Gate Bipolar Transistors, SiC-based vertical power diodes and backside illuminated CMOS imaging sensors. It is now on the verge of being integrated in key annealing process steps in next generation CMOS and memory devices manufacturing. This invited paper presents recent experimental and simulation work involving sub-µs laser annealing for a wide range of applications, from contact formation to material modification and 3D sequential integration.

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Thin Film Deposition for Front End of Line

Cited by 10 publications

References 73 publications

Fluorene intercalated graphene oxide based CoQ10 imprinted polymer composite as a selective platform for electrochemical sensing of CoQ10

Fluorene intercalated graphene oxide based CoQ10 imprinted polymer composite as a selective platform for electrochemical sensing of CoQ10

Advanced process control by machine learning-based virtual metrology for high product mix manufacturing

(Invited) Laser Thermal Annealing for Low Thermal Budget Applications: From Contact Formation to Material Modification

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