Thermomechanical modeling of 3D electronic packages

Sri-Jayantha, Sri M.; McVicker, Gerard; Bernstein, K.; Knickerbocker, John

doi:10.1147/jrd.2008.5388568

Cited by 66 publications

(33 citation statements)

References 9 publications

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“…This too stems from the fundamental mismatch of CTE's between TSV metallization such as copper, and the surrounding silicon envelope. Several researchers have studied various aspects of this problem [56][57][58][59][60][61][62][63]. A few of these findings are discussed here.…”

Section: Thermo-mechanical Integrity and Reliabilitymentioning

confidence: 99%

“…Modeling using FEM (finite element modeling) has been conducted to enable technologists to get early insights [56]. Complexity in the building of the model arises due to the presence of organic carriers, thermal interface materials, and chip underfill materials, which inherently do not lend themselves to a simple linear elastic problem.…”

Section: Thermo-mechanical Integrity and Reliabilitymentioning

confidence: 99%

“…Complexity in the building of the model arises due to the presence of organic carriers, thermal interface materials, and chip underfill materials, which inherently do not lend themselves to a simple linear elastic problem. Additionally, the pulsing of hotspots during random workloads must be considered, which further complicates the problem [56]. The thermal characteristics of 3D stacks can actually exacerbate reliability concerns, which is why thermal management of 3D structures is an important field of study [57].…”

Section: Thermo-mechanical Integrity and Reliabilitymentioning

confidence: 99%

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3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Section: Thermo-mechanical Integrity and Reliabilitymentioning

confidence: 99%

Section: Thermo-mechanical Integrity and Reliabilitymentioning

confidence: 99%

Section: Thermo-mechanical Integrity and Reliabilitymentioning

confidence: 99%

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3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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“…Efficient heat dissipation in IC packages is crucial to support the packing density and performance scaling of future systems [2,3]. The ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities.…”

Section: Introductionmentioning

confidence: 99%

Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Madhour

Zervas

Schlottig

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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Abstract-Three-dimensional (3D) stacking of integratedcircuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single-and twophase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65.

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“…However, for processor applications, 3D-stacking requires a tradeoff between signal integrity and power supply efficiency, and cooling [4,5]. Furthermore, 3D-stacking adds assembly risk to already challenging processor packaging.…”

Section: Introductionmentioning

confidence: 99%