Thermal treatment for preventing void formation on directly-bonded InP/Si interface

Abstract

The surface conditions of thin film InP epitaxial layers transferred to a Si substrate have been investigated in terms of void size, density, and area occupied by the voids, by changing the annealing temperature and ramping periods to reach the annealing temperature of 400 °C. Through a long ramp annealing time of 45 h, the voids generated were downsized by up to two orders of magnitude, and the total number of voids also greatly decreased compared that for the typical annealing process at 400 °C. This resulted in a reduction of the InP surface area occupied by voids from 3.96 to 0.03%. Then, successful fabrication of void-free 50 mm InP/Si substrates without forming any outgassing channels has been demonstrated.

Lasing Characteristics of 1.2 µm GaInAsP LD on InP/Si Substrate

“…In contrast, J th was increased with the cavity length for the InP/Si substrate. This is due to additional internal losses by the length of cavity, such as thermal resistance, voids at the interface of InP and Si, and also, most importantly, the difference in the thermal expansion coefficient between InP and Si . Although these differences are expected, lasing operation for 1.2 μm GaInAsP on the InP/Si substrate was successfully obtained, which suggests further research and a reduction of J th in the future.…”

“…Therefore, in the present experiment, especially prior to MOVPE growth, the preparation of wafer direct bonded InP/Si substrate is necessary to achieve an increase in bonding strength, cleanliness and surface roughness without deformation for double heterostructure crystal growth. Among the various bonding techniques involved in our study, we have employed hydrophilic wafer bonding, which provides advantages such as surface roughness, cleanliness and uniform bonding . Figure shows the number of stages involved in the formation of the InP/Si substrate.…”

Current-injected light emission of epitaxially grown InAs/InP quantum dots on directly bonded InP/Si substrate

“…19) This chemical cleaning process is considered to remove thermally unstable hydrocarbons from the surface, which is necessary to prevent the formation of voids at the bonded interface. 20,21) Both the GaInAs/InP/GaInAs layer and the Si substrate surfaces were chemically cleaned with a solution of H 2 SO 4 : H 2 O 2 : H 2 O ¼ 3 : 1 : 1 to obtain a thin film InP layer and hydrophilize both the layer and Si surface, 22,23) followed by rinsing in deionized (DI) water. Through this process, OH-groups are absorbed on the surface, which is considered to result in the hydrophilicity.…”

Geometry and Thermal Stress Analysis of In-plane Outgassing Channels in Al2O3-Intermediated InP (Die)-to-Si (Wafer) Bonding

“…12 Several approaches have been investigated to suppress the interfacial void density. 10,[13][14][15][16][17] Liang et al 10 used vertical outgassing channels (VOCs) in InP-on-SOI bonding to absorb and out-diffuse the gas by-products into porous buried SiO 2 layer. Although void-free bonding has been achieved, these absorbed gases were found to cause serious film delamination at high temperature post-bonding processes.…”

“…Although void-free bonding has been achieved, these absorbed gases were found to cause serious film delamination at high temperature post-bonding processes. 13 Zhang et al 14 and Matsumoto et al 15 adopted long post-bonding annealing and temperature ramp time, respectively, to achieve minimized void size and density. However, long annealing time inhibits the fabrication throughput and therefore may not be an optimal solution.…”