Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip

Yu, Thomas Edison; Yoneda, Tomokazu; Chakrabarty, Krishnendu; Fujiwara, Hideo

doi:10.1109/ats.2007.4388007

Cited by 4 publications

(14 citation statements)

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“…The results show that (i) the test application time obtained using the proposed method is in most cases less than that using [10]; (ii) the proposed method provides solutions even under tight temperature constraints, including situations where [10] fails to find a solution.…”

Section: Introductionmentioning

confidence: 86%

“…The computation time for test scheduling is reduced by the use of a computationally tractable thermal-cost model which considers the thermal effects between cores, and a heuristic bin-packing algorithm for test scheduling. Simulation results in [10] showed that, while the proposed solution is useful in many situations, especially for wide SOC-level TAMs, it is relatively ineffective under tight thermal constraints and narrow TAM widths.…”

Section: Limitations Of Related Prior Workmentioning

confidence: 96%

“…Such an assumption is too restrictive in practice due to the temporal and spatial variation of hot spots and chip temperatures [9]. Furthermore, it was assumed that temperature influences between cores are negligible, which was shown in [10] to be too optimistic and unrealistic.…”

Section: Limitations Of Related Prior Workmentioning

confidence: 99%

“…A thermal-aware TAM/wrapper co-optimization and test scheduling method for SoCs with a flexible-width TAM architecture was presented in [10]. This approach uses cycle-accurate power profiles for accurate thermal simulation.…”

Section: Limitations Of Related Prior Workmentioning

confidence: 99%

“…Due to the effects of thermal capacitance, the correlation between actual temperature and chip power consumption is quite low in practice. Thus, a thermal-aware TAM/wrapper co-optimization and test scheduling method for SoCs was presented in [10].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

A¹,

Yoneda²,

Chakrabarty³

et al. 2009

2009 Asia and South Pacific Design Automation Conference

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We present a thermal-aware test-access mechanism (TAM) design and test scheduling method for system-on-chip (SOC) integrated circuits. The proposed method uses cycle-accurate power profiles for thermal simulation; it also relies on test-set partitioning, test interleaving, and bandwidth matching. We use a computationally tractable thermal-cost model to ensure that temperature constraints are satisfied and the test application time is minimized. Simulation results for the ITC'02 SOC Test Benchmarks show that, compared to prior thermal-aware test-scheduling techniques, the proposed method leads to shorter test times under tight temperature constraints.

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Section: Introductionmentioning

confidence: 86%

Section: Limitations Of Related Prior Workmentioning

confidence: 96%

Section: Limitations Of Related Prior Workmentioning

confidence: 99%

Section: Limitations Of Related Prior Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

A¹,

Yoneda²,

Chakrabarty³

et al. 2009

2009 Asia and South Pacific Design Automation Conference

Self Cite

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RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC

Hussin

Yoneda

et al. 2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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This paper investigates the challenges of a 3D-stacked system-on-chip testing, especially in terms of thermal problem. It is known that test power can be more than twice the intended power dissipation of the chip in the functional mode, for a single die. This problem is exacerbated when more than one dies are stacked on top of each other in a single package. Without proper test strategies, the thermal limit could be exceeded during test and this could permanently damage the possibly good chips. Using a heuristic approach, we proposed a set of rules that need to be followed when scheduling the core tests of each chip layer. These rules are based on the initial findings of 3D-chip test simulation using a commercial thermal simulation tool. Using these simple rules, it was found that up to 40% reduction in the peak temperature can be achieved when the thermal-aware test scheduling technique is employed.

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Thermal-Aware Test Scheduling Using On-chip Temperature Sensors

Yao

Saluja

Ramanathan

2011

2011 24th Internatioal Conference on VLSI Design

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With scaling of technology and increasing design sizes, thermal issues are emerging to be one of the major concerns for modern Very-Large-Scale Integration (VLSI) testing due to both increasing power densities and higher reliability requirements. However, in all existing thermal-aware test scheduling research, test schedule is computed a priori as a static schedule using an estimate of the power consumed by each test. Due to the popular peak power model and increasing process variations, estimated test power values can be far from the actual power consumption. Consequently, the thermal profile of the chip estimated during off-line scheduling can be substantially different from that during actual testing. In this paper, we propose a dynamic thermal-aware test scheduling method using on-chip temperature sensors. We first define a test architecture that supports dynamic test scheduling and then develop a scheduling algorithm. Next, we perform simulation studies on ITC'02 benchmarks. Our simulation results show that the performance of the thermalaware test scheduling can be substantially improved with the help of on-chip temperature sensors, especially for chips with many cores.

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Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip

Cited by 4 publications

References 0 publications

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC

Thermal-Aware Test Scheduling Using On-chip Temperature Sensors

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