Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

A, Yu; Yoneda,; Chakrabarty, Krishnendu; Fujiwara,

doi:10.1109/aspdac.2009.4796577

Cited by 7 publications

(2 citation statements)

References 11 publications

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“…For example, previous use conditions for PVT were 0 to 100C, but now have increased to -40 to +120C to support IoT, Autonomous Manuscript August 1, 2018; revised April 12, 2019. Rafi M Saied is a Senior Staff Engineer at Intel Corp. in Folsom, USA (e-mail: rafi.saied@intel.com) market etc [2]. These extreme conditions required additional checks to ensure functionality is not affected.…”

Section: Introductionmentioning

confidence: 99%

Building Robust Designs for Best Process Scaling

Saied¹,

Wen²

2019

IJMO

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The demand for Multi Giga Hertz high performance microprocessors continues to increase along with the need to support many modes of operations under multiple conditions. The demand from mission critical servers and data farms require that these are robust, reliable and perform at peak performance under all conditions. The devices must be able to work at high speeds to meet the performance demands, quickly and reliably which causes increasing challenges in hardware designs to ensure the machine is both robust and reliable in diverse conditions. There are many aspects involved in performance verification of design such as process technology, voltage, temperature, library design, routing, and the system conditions. In order to model all of this correctly, design has to be verified under multiple PVT (Process, voltage and Temperature) conditions. We need to account for the variation that comes with different voltages and temperature conditions [1], for example how the device behaves at 0.55V vs. 1.1v. In this paper we show how some of these challenges can be addressed through Best Design techniques, Mode of work, and methodology changes to get the design that is robust across different PVTs and reduce process variation impact.

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Section: Introductionmentioning

confidence: 99%

Building Robust Designs for Best Process Scaling

Saied¹,

Wen²

2019

IJMO

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“…The power density for a System-on-Chip (SoC) during test is considerably higher compared to the normal operation [4][5][27][28] and so is the risk of overheating. Therefore, the temperature of the chip under test should be taken into account when designing the test process [5,27]. Traditionally, thermal-aware test schedules are optimized to achieve minimum test application time while avoiding any overheating.…”

Section: Introductionmentioning

confidence: 99%

Process-Variation and Temperature Aware SoC Test Scheduling Technique

2013

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High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoCs). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC'02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.

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Manna¹,

Mathew²

2019

Design and Test Strategies for 2d/3d Integration for NoC-based Multicore Architectures

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Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints

Cited by 7 publications

References 11 publications

Building Robust Designs for Best Process Scaling

Building Robust Designs for Best Process Scaling

Process-Variation and Temperature Aware SoC Test Scheduling Technique

Alternative Approaches

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