Thermal instabilities in high current power MOS devices: experimental evidence, electro-thermal simulations and analytical modeling

Spirito, P.; Breglio, G.; d’Alessandro, V.; Rinaldi, N.

doi:10.1109/miel.2002.1003144

Cited by 42 publications

(25 citation statements)

References 7 publications

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“…showing that instability does not depend necessarily on a 'positive current coefficient with respect to temperature of the device', as other authors have reported [4].…”

Section: (T) = V(t) ı T (V(t)t (T))− K 0 (T (T))+2 K C (T (T))[cos( supporting

confidence: 57%

Electrothermal stability of uniform arrays of one‐port elements

Storti-Gajani

Premoli

Brambilla

2008

Circuit Theory & Apps

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SUMMARYPower electronic elements are often built employing arrays of devices designed to evenly share high currents over a large number of single devices. In some situations, mismatch in current sharing can occur causing temperature differences between elements of the array. These differences can trigger electrothermal instability phenomena and even device destruction. In this paper, we consider the electrothermal dynamic behavior of arrays composed of identical one-port elements. We first introduce a simplified model of the thermal paths and of the elements composing the array that allows the analysis of the behavior of the electrothermal system. Then, we investigate from a mathematical standpoint dynamic effects governing current sharing and possible situations causing hot spots with consequent device destruction. These results are compared with simulations of detailed non-linear models confirming predictions given by the simplified model.

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“…showing that instability does not depend necessarily on a 'positive current coefficient with respect to temperature of the device', as other authors have reported [4].…”

Section: (T) = V(t) ı T (V(t)t (T))− K 0 (T (T))+2 K C (T (T))[cos( supporting

confidence: 57%

Electrothermal stability of uniform arrays of one‐port elements

Storti-Gajani

Premoli

Brambilla

2008

Circuit Theory & Apps

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“…Because of the non-uniform lateral heat flow, however, there can still be temperature non-uniformities in the structure. Such effects require the use of distributed electrothermal network for accurate modeling, as seen in [135,139].…”

Section: Electrothermal Soamentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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“…The transition between the two operational regions is referred to as the point of zero temperature coefficient (ZTC in Fig. 5) [8]. Since some hundred thousand cells are connected in parallel to make up a PowerMOSFET, operation of the transistor left of the ZTC is thermally unstable.…”

Section: B Linear and Short-circuit Operationmentioning

confidence: 99%

“…In the transient regime, current crowding takes place, leading to the formation of hot- spots and temperature gradients within the chip. Whereas for high-voltage devices and older technologies thermally unstable behavior was typically confined to a region of negligible interest for most application purposes, recent investigations have shown that this range broadens for reduced channel length [8]. For that reason, operation as linear regulators is particularly critical for low-voltage devices of modern generation, such as the ones used within the 42-V-PowerNet.…”

Section: B Linear and Short-circuit Operationmentioning

confidence: 99%

Reliability analysis and modeling of power MOSFETs in the 42-V-PowerNet

Castellazzi

Gerstenmaier

Kraus

et al. 2006

IEEE Trans. Power Electron.

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Abstract-This paper analyzes the operation of PowerMOSFETs in the 42-V-PowerNet and shows that very stressful conditions are encountered, which can lead to severe reliability problems. To enable thorough investigations by circuit simulations an accurate physics-based compact model of the devices is proposed: it includes all important electrothermal effects relevant to the description of the observed failure mechanisms. By means of an advanced thermal-modeling approach, multichip assemblies can be accurately described, including mutual heating effects between neighboring devices. Some properly chosen examples demonstrate the validity of the model and its usefulness for reliability investigations.Index Terms-Electrothermal effects, modeling, power metal-oxide semiconductor field-effect transistors (MOSFETs), reliability.

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Thermal instabilities in high current power MOS devices: experimental evidence, electro-thermal simulations and analytical modeling

Cited by 42 publications

References 7 publications

Electrothermal stability of uniform arrays of one‐port elements

Electrothermal stability of uniform arrays of one‐port elements

High-Voltage and Power Transistors

Reliability analysis and modeling of power MOSFETs in the 42-V-PowerNet

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