Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors

Puttaswamy, Kiran; Loh, Gabriel H.

doi:10.1109/hpca.2007.346197

Cited by 134 publications

(74 citation statements)

References 34 publications

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“…Another work utilizes various microarchitectural techniques to control the thermal hotspots in 3D MPSoCs via thermal herding [100]. This technique explores different architectural disciplines by spitting several microarchitectural blocks between the different layers of 3D MPSoC to enhance the throughput while controlling the thermal hotspots such as, register file splitting.…”

Section: Design-time Power and Thermal Optimizationsmentioning

confidence: 99%

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

Kim

Sabry

Ruggiero

et al. 2015

Handbook on Data Centers

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Section: Design-time Power and Thermal Optimizationsmentioning

confidence: 99%

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

Kim

Sabry

Ruggiero

et al. 2015

Handbook on Data Centers

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“…To create this map we examined a publicly released die photo of the 45 nm Penryn and produced a floorplan based on the work from Puttaswamy and Loh [12] We then divided the logical pipeline stages of the floorplan by area and generated a power distribution. This distribution was created by dividing a total power dissipation of 54 watts for a dual-core version into the component stages for two processors.…”

Section: A Power Mapsmentioning

confidence: 99%

A study of stacking limit and scaling in 3D ICs: an interconnect perspective

Healy

Lim

2009

2009 59th Electronic Components and Technology Conference

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An examination of large-scale stacking of 3D integrated ICs from a power-supply and thermal reliability perspective is presented. Noise characteristics and scaling issues related to through-silicon-via (TSV) size and pitch as well as other power-supply topology characteristics are included. Thermal simulations are carried out assuming the use of micro-fluidic heatsinks to provide cooling to systems with power dissipation of up to 525 watts and 46 integrated silicon tiers. Results indicate that these large systems are feasible given sufficient planning. Power-delivery-bump pitch is identified as the most important factor influencing IR-drop and dynamic noise. Contact resistance also may become a major limiting factor. I. IntroductionThe shift to the multi-core era has increased demand on the memory bandwidth of high performance processor systems. 3D integration of memory and processors has emerged as a potential solution to the memory bandwidth problem. However, there are several unanswered questions regarding 3D integration. In this work we study integration scaling from a power-supply and thermal perspective. As the number of tiers in a 3D system increase, the uppermost tiers become separated from the power supply bumps by increasing resistance and inductance. The cause of these parasitics is the through-silicon vias (TSVs) that provide communication between tiers. Additionally, increasing integration quickly raises the volumetric power density of the IC stack.The largest factor creating transient noise is the so-called "first droop" noise that results from the interaction of the inductance in the package and the on-chip decap during sleep transitions. Power gating due to sleep transitions causes large transient changes in the current demand in the power supply network. In the case of 3D systems the TSVs add inductance of their own to that which naturally exists in the package.Thermal impacts are a major factor that must be considered when designing 3D systems. For the purpose of maximum 3D integration studies standard air-cooled heatsinks will be unable to cope with the power density of these systems. Recent work has focused on implementing micro-fluidic channels [1] onto the backs of 3D stacked ICs for the purpose of removing heat using liquid-phase fluids. The heat removal capacity of these systems is very promising. In this work we assume that microfluidic heatsinks are used to dissipate heat, and design our power distribution model around this assumption.

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“…However, one side effect of 3D designs is the increase in power density on parts of the chip due to the stacking of active power dissipation devices, which result in thermal hotspots [2]. The temperature increase may limit the maximum operating frequency of the chip, and thereby degrade the system performance.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, our approach achieves 9.43% power saving and 14.88% delay reduction. Keywords: 3D Network-on-Chip, MSP, thermal, mapping Classification: Electron devices, circuits, and systems IEICE Electronics Express, Vol.13, No.7,[1][2][3][4][5][6][7][8][9] Hardware/Software Codesign (1988). …”

mentioning

confidence: 99%

MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints

Feng

et al. 2016

IEICE Electron. Express

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Three dimensional Network-on-chip (3D NoC) is proposed as an effective architecture to optimize system performance. However, thermal issues bring significant challenges on 3D NoC due to high power density. In this paper, we propose a 3D matrix synthesis problem (MSP) based thermalaware mapping approach under performance constraints for 3D NoC architecture to realize temperature equilibrium and achieve better performance. Genetic algorithm is taken in the approach to obtain the optimal placements. Experimental results show that the proposed approach can achieve a temperature deviation of 45.3% on average compared with the state of art thermal optimization approaches. Moreover, our approach achieves 9.43% power saving and 14.88% delay reduction. Keywords: 3D Network-on-Chip, MSP, thermal, mapping Classification: Electron devices, circuits, and systems IEICE Electronics Express, Vol.13, No.7,[1][2][3][4][5][6][7][8][9] Hardware/Software Codesign (1988). References

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Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors

Cited by 134 publications

References 34 publications

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

Power-Thermal Modeling and Control of Energy-Efficient Servers and Datacenters

A study of stacking limit and scaling in 3D ICs: an interconnect perspective

MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints

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